Patent
1997-07-30
1999-01-26
Lim, Krisna
395561, 395595, G06F 930
Patent
active
058646906
ABSTRACT:
An apparatus and method for improving the execution speed of programs including register generic micro instructions within a pipeline processor is provided. The processor contains a translator and a control ROM, both of which may produce micro instructions associated with the program. When a micro instruction is produced by the control ROM, and when the micro instruction contains register generic operands, the micro instruction is placed within a ROM instruction queue. While in the instruction queue, register specific operands may be placed within the micro instruction. Thus, by the time the micro instruction reaches an instruction register, the micro instruction is ready for execution by later stages in the pipeline, without requiring a hole or delay in the pipeline to fill in register specific operands.
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patent: 5247624 (1993-09-01), Koumoto et al.
patent: 5471591 (1995-11-01), Edmundson et al.
patent: 5673427 (1997-09-01), Brown et al.
Henry G. Glenn
Parks Terry
Huffman James W.
Integrated Device Technology Inc.
Lim Krisna
Vu Viet
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