Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-13
2003-07-01
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185210, C365S185250
Reexamination Certificate
active
06587378
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to the memory units in data processing systems used to store logic bits. More specifically, the present invention relates to the operation of a semiconductor memory generally referred to as a Flash memory or Flash memory unit.
2. Background of the Invention
The Flash memory units have received wide application in electronic devices as a non-volatile memory. The hereto-fore most common memory unit was a random access memory (RAM) unit. The RAM memory units are volatile and must be refreshed periodically. In addition, the RAM memory unit must be reloaded after each shut-down of the memory unit. In contradistinction, A Flash memory unit retains the information during device shut-down and does not have to be reloaded.
Referring to
FIG. 1
, a cross-sectional view of a Flash memory cell
10
is shown. The Flash memory cell
10
includes a substrate (well) region
11
in which a source electrode
12
and a drain electrode
14
are formed. The source electrode
12
and the drain electrode
14
are separated by a channel region
15
. Opposite the channel region
15
and separated from the channel region
15
by a tunnel oxide layer
18
is a polysilicon floating gate
17
. A polysilicon control gate
17
is separated from the floating gate
17
by an interpolysilicon dielectric layer
19
. Bias voltages can be applied to the well (substrate)
11
, to the source electrode
12
, to the drain electrode
14
, and to the control gate
17
.
The Flash memory cell
10
can be biased to function as a memory cell in the following manner. When the source electrode
12
is biased to 0 potential, the well region
11
is biased to 0 potential, the drain electrode
14
is biased to an intermediate voltage, and the control gate is biased to a high potential, then electrons migrate to and are stored on the floating gate
16
. The storage of electrons on the floating electrode
16
provides the write operation for the Flash memory cell
10
that can be considered a representation of the stored logic state. When the source electrode
12
and the well region
11
are biased to 0 potential, the drain is electrode
14
is biased to a small potential, and the control gate
17
is biased to approximately the intermediate potential, stored charge on the floating electrode
16
controls the current through the channel and the “logic state” of the device can be determined. When the source electrode
12
and the drain electrode
14
are allowed to “float”, a negative high voltage is applied to the control gate
17
, and the well is biased to a positive high potential, the “logic state” of the Flash cell
10
is erased. That is, any charge stored on the floating gate will be removed. According to one embodiment, the presence of charge stored on the floating gate
16
is defined as a “logic 0 state” and the absence of charge stored on the floating gate is defined as a “logic 1 state”. (As will be clear to those skilled in the art of Flash memory units, the erase operation can be somewhat more complex and can involve at least one “compact” operation. The “compact” operation is not necessary to the understanding of the present invention.)
While using present technology, the non-volatile nature of the present invention can be understood as a relative term. Over long periods of time, the charge on the floating gate
16
can be lost. The mechanisms for the loss of charge can include thermal migration, process irregularities, environmental conditions, etc. Therefore, when the logic signals stored in a Flash memory unit are unchanged for long periods of time, the “logic state” stored in the Flash memory unit can eventually be compromised.
A need has therefore been felt for apparatus and an associated method having the feature that the integrity of the logic signals stored in a Flash memory unit can be tested. It is another feature of the present invention that the integrity of the logic signals stored in a Flash memory unit is automatically stored during initiation of the operation. It is yet a further feature of the present invention to determine the integrity of a flash memory unit for an intermediate charge level on each cell between the originally stored charge level and the charge level required to establish the logic state of a memory cell. It is a still further feature of the present invention, when the integrity test for an intermediate cell charge logic state fails, to test the integrity of the Flash memory cells for typical read conditions. It is yet another feature of the present invention, when test for the intermediate Flash memory cell logic state and the test for logic state under typical read conditions is successful, to refresh the charge on the Flash memory cell that failed the intermediate charge level logic signal integrity test. It is a still further feature of the present invention to abort the use of the Flash memory cells that fail the typical read condition logic signal test.
SUMMARY OF THE INVENTION
The aforementioned and other features can be accomplished, according to the present invention, by providing the Flash memory cell with a test condition in which a logic 0 can be read from the Flash test cell only when the charge stored on the floating gate is greater than that normally required to read a logic “0” and the amount of charge is less than the amount of charge stored on the gate stored during a write logic “0” operation. In this manner, a determination can be made whether the charge on the Flash memory cell has decayed beyond a preselected amount. When the charge has decayed below the preselected amount on a Flash memory cell floating gate, the charge on the floating gate is refreshed. In practice, the entire Flash memory is accessed in the test mode of operation and a test (read) checksum is calculated. When the test (read) checksum verifies the integrity of the contents of the Flash memory unit, no further action is necessary. When the checksum does not verify the integrity of the contents of the Flash memory unit, a normal (read) checksum is performed. When the normal checksum does not verify the contents of the Flash memory unit, then the activity is aborted. When the normal (read) checksum verifies the integrity of the contents of the Flash memory unit, then the result of a normal read and a test read from each cell are compared. When the test and normal read of a Flash memory cell provide the same result. When the test and the normal read of a Flash memory cell are different, the cell is then refreshed, i.e., the stored charge is once again written on the floating gate of the Flash memory cell. In this manner, a margin of safety can be obtained for the Flash memory unit.
REFERENCES:
patent: 6282120 (2001-08-01), Cernea et al.
patent: 6411549 (2002-06-01), Pathak et al.
Crosby Robert M.
Dunn Clyde F.
Hassan Mohammed A.
Love Andrew M.
Brady W. James
Hoang Huan
Holloway William W.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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