Apparatus and method for reducing power consumption in a compute

Details Apparatus and method for reducing power consumption in a compute Apparatus and method for reducing power consumption in a compute

1996-02-29

1997-04-22

Sheikh, Ayaz R.

G06F 1500

Patent

active

056236778

ABSTRACT:
A method and apparatus for reducing the power consumption of a processor in a computer system where a programming structure running on the processor determines when the processor is in an inactive state to cause clocking signals and the power supply to be disabled to the processor. The processor is again coupled to the power supply and the clock signals in response to a periodic interrupt signal, a non-periodic interrupt or a bus request from a peripheral device. Thereafter, the programming structure signals the control logic again when the processor reenters the inactive state, such that the control logic disables the clock signals and decouples the power supply to the processor when the processor returns to the inactive state. The method is extended to offer the ability to shut down the processor from programming structures running on alternate masters or subsystem controllers within the same system.

REFERENCES:
patent: 4870570 (1989-09-01), Satoh et al.
patent: 5167024 (1992-11-01), Smith et al.
patent: 5239652 (1993-08-01), Seibert et al.
patent: 5392437 (1995-02-01), Matter et al.

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