Apparatus and method for reducing pitch in an integrated...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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C257S773000, C257SE23067, C257SE23145

Reexamination Certificate

active

08008781

ABSTRACT:
An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.

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patent: 2008/0099885 (2008-05-01), You et al.
patent: 2008/0149379 (2008-06-01), Nagase et al.

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