Apparatus and method for reducing erased threshold voltage distr

Details Apparatus and method for reducing erased threshold voltage distr Apparatus and method for reducing erased threshold voltage distr

1994-12-06

1997-02-04

Zarabian, Amir

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 36518533, G11C 700

Patent

active

056005938

ABSTRACT:
A flash memory system and method for providing an array of erased flash memory cells having a reduced dispersion of erased threshold voltages. The cells of the system are erased in bulk, preferably utilizing some form of cold electron injection, and the cells are tested to determine whether the erased threshold voltage falls between a predetermined target maximum threshold voltage and a predetermined target minimum threshold voltage. In the event one or more cells has been over erased so that the measured threshold voltage is less than the target minimum values, all of the cells are lightly programmed so as to increase the actual threshold voltage. The light programming is repeated until all of the cells have an actual threshold voltage that exceeds the target minimum but is less than the target maximum.

REFERENCES:
patent: 5172338 (1992-12-01), Mehrorta
patent: 5329487 (1994-07-01), Gupta
patent: 5386388 (1995-01-01), Atwood
patent: 5402370 (1995-03-01), Fazio
patent: 5424993 (1995-06-01), Lee
Kuniyoshi Yoshikawa et al., "Comparison of Current Flash EEPROM Erasing Methods: Stability and How to control", 1992, pp. 595-598, IEDM Technical Digest.
K. Oyama et al., "A Novel Erasing Technology for 3.3V Flash Memory with 64Mb Capacity and Beyond", 1992, pp. 607-610, IEDM Technical Digest.
Seiji Yamada et al., "A Self-Convergence Erasing Scheme For a Simple Stacked Gate Flash EEPROM", 1991, pp. 307-310, IEDM Technical Digest.

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