Patent
1994-09-28
1997-09-02
Harvey, Jack B.
395383, 395389, G06F 1300
Patent
active
056641354
ABSTRACT:
An improved computer architecture and instruction set that reduces the delays produced by branch instructions. The invention utilizes a branch processor having a branch memory for storing information specifying a plurality of branch instructions that are contained in a code sequence. The branch memory stores information specifying the target address of each branch instruction and the location of the branch instruction with respect to the beginning of the code sequence. The branch processor receives the results of the various comparisons that determine if the conditions associated with the various branches stored in the branch memory are satisfied. The branch processor preferably stores the identity of the branch that is closed to the beginning of the code sequence for which the condition associated therewith has been satisfied. This branch will be referred to as the highest branch enabled. The actual branching operation is carded out in response to the receipt of an execute branch instruction which specifies one or more of the branches stored in the branch memory. If one of the branches specified in the execute branch instruction matches the highest branch enabled, then the code sequence continues at the target address of the highest branch enabled.
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patent: 3577189 (1971-05-01), Cocke et al.
patent: 4991080 (1991-02-01), Emma et al.
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H. C. Young and J. R. Goodman, "A Simulation Study of Architectural Data Queues and Prepare-to-Branch Instruction", Proceedings of the IEEE International Conference on Computer Design, VLSI in Computers ICCD '84, Port Chester, NY, 1984, pp. 544-549.
Jack W. Davidson and David B. Whailley, "Reducing the Cost of Branches by Using Registers", Department of Computer Science, University of Virginia, 1990 IEEE.
Kathail Vinod
Schlansker Michael S.
Harvey Jack B.
Hewlett--Packard Company
Travis John
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