Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1999-09-13
2001-04-24
Mancuso, Joseph (Department: 2623)
Image analysis
Applications
Manufacturing or product inspection
C348S129000
Reexamination Certificate
active
06222936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to techniques for detecting and reducing defects formed on a wafer during submicron lithography.
2. Description of Related Art
Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects on integrated circuits. Defects are the primary “killers” of devices formed during manufacturing, resulting in yield loss. Hence, defect densities are monitored on a wafer to determine whether a production yield is maintained at an acceptable level, or whether an increase in the defect density creates an unacceptable yield performance. Hence, the detection and monitoring of defects is critical to maintaining an acceptable yield.
As device geometries shrink into the sub-half micron regime, controlling and reducing defect levels become increasingly important in both research and development and manufacturing environments. Any delay in addressing the causes and cures of these yield killers can prolong the development cycle and production release of new product technologies. However, defect evaluation for a new lithography process on product wafers is difficult due to metrology limitation, substrate noises and previous layer defects. This problem is particularly pronounced for backend layers where differences in the metal grain sizes and reflectivity can confound defect inspection tools and can be picked up as false defects. Often yield learning is long delayed awaiting sort data, before lithographers can determine the beneficial effects of proposed manufacturing improvements.
During the qualification stage of a new process technology or a new product, a minimum sort yield level (typically 15 to 20%) must be achieved in order for the new product or the new process to be considered production worthy. Often, managers use the early yield indicator to decide whether to utilize a new product design or a new process technology. However, IC device yield is largely influenced by defects in the fabrication process. Defects are commonly divided into two categories by yield engineers: systematic and random. Systematic defects are anomalies resulting from an unoptimized process flow, from design rule violations or a mismatch between process and design in the worst case. However, once a systematic defect is identified, its impact on product yield and performance is predictable and therefore can be corrected within a short time. On the other hand, random defects are due to contamination from process and equipment. They occur irregularly and tend to be unpredictable. Elimination of these random defect excursions, if not controlled and monitored properly, become more difficult and can confound systematic yield issues. If random defects cannot be reduced in a timely manner, a new process can be jeopardized and consequently lead to a delay in new product introduction.
In the photolithography area, in-line defect monitoring of production wafers becomes more difficult with each successive masking layer. Film sensitivities, topographic effects and previous layer defects can make the determination of the existence or magnitude of photo process defect occurrence almost impossible. This is particularly true for the backend process where multi-layer metallization and chemical mechanical polish (CMP) are used. The effort to optimize a lithographic process can be statistically insignificant due to small sample size, or inconclusive if impacted by other non-photo variables.
DISCLOSURE OF THE INVENTION
There is a need for an arrangement for reducing defects in a semiconductor fabrication process, more specifically an arrangement for optimizing a lithographic process to reduce defects and to qualify the optimized lithographic process for production.
There is also a need for an arrangement for detecting random defects occurring during photolithography processing, and for monitoring the random defects to optimize the lithographic process.
These and other needs are attained by the present invention, where a semiconductor fabrication process, for example an I-line lithographic process, is optimized, where a pattern formed on a silicon wafer using a semiconductor fabrication process simulating a prescribed processing specification is inspected for defects. The detected defects are then classified, enabling generation of an alternative processing specification. The alternative processing specification is then tested by forming patterns on different wafers using the attenuated processing specification (e.g., split-series testing), and then analyzing the patterns on the different wafers relative to the prescribed processing specification. The testing thus enables qualification of the alternative processing specification for production of semiconductor products.
According to one aspect of the present invention, a method of reducing defects in a semiconductor fabrication process comprises forming a pattern on a first silicon wafer using the semiconductor fabrication process according to a prescribed processing specification, inspecting the pattern on the first silicon wafer to detect a first defect, developing an alternative processing specification relative to the prescribed processing specification based on the first defect, forming the pattern on a second silicon wafer using the semiconductor fabrication process according to the alternative processing specification, comparing respective characteristics of the patterns on the first and second silicon wafers, and changing the lithographic process to include the alternative processing specification based on the comparing step. The formation of the pattern on the first silicon wafer using the semiconductor fabrication process according to the prescribed processing specification enables precise analysis of the prescribed processing specification forming the pattern, without introducing additional variables that may otherwise be present during fabrication of a complete integrated circuit product. In addition, the inspecting of the pattern on the first silicon wafer to detect a first defect may be implemented as a short loop test, where defect causes related to the prescribed processing specification can be efficiently identified, including both killer defects directly affecting yield and non-killer defects that do not necessarily cause potential yield problems but which may affect defect stability. The comparison of the respective characteristics of the patterns on the first and second wafers also enables the alternative processing specification to be qualified relative to the prescribed processing specification in an efficient manner.
Another aspect of the present invention includes a method of reducing defects in a lithographic process, comprising forming a resist pattern on a first silicon wafer using the lithographic process according to a prescribed processing specification, inspecting the resist pattern on the first silicon wafer to detect a first defect, developing an alternative processing specification relative to the prescribed processing specification based on the detected first defect, forming the resist pattern on a second silicon wafer using the lithographic process according to the alternative processing specification, comparing respective characteristics of the resist patterns on the first and second silicon wafers, and changing the lithographic process to include the alternative processing specification based on the comparing step. Inspection of the resist pattern on the first silicon wafer provides precise analysis of the prescribed processing specification for the lithographic process, enabling rapid identification of defect causes for corrective action. In addition, comparing the respective patterns (e.g., split-series testing) enables rapid verification of the corrective action and qualification of the alternative processing specification for production.
Still another aspect of the present invention provides a system for reducing defects in a photolithography manufacturing process, comprising a photocluster cell system configured for simulat
Bains Gurjeet S.
Orth Jonathan A.
Phan Khoi A.
Steele David A.
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Mancuso Joseph
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