Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1997-08-27
2001-11-27
Luther, William (Department: 2664)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S262000
Reexamination Certificate
active
06324224
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and a method for receiving data and, more particularly, to a data receiver and a data receiving method for receiving multi-component signals representing values for several data bits.
BACKGROUND OF THE INVENTION
In the U.S.A., digital broadcasting bas already been started. Also in Europe, the organization for standardization “Digital Video Broadcasting (DVB)” has been formed to introduce digital TV broadcasting and its standard system is now being made. Such digital broadcasting is described, for example, in “Europe set to start digital satellite broadcasting in 1996 after successful U.S. nationwide services”, NIKKEI ELECTRONICS 1.15, 1996 (No. 653), pp. 139-151.
In digital broadcasting and in other types of data transmission, it is desirable to minimize the power in the signal. This in turn reduces the ratio of signal power to noise power, and increases the probability of transmission errors. An error-correcting code is used to obtain a coding gain which compensates for this effect. Ordinarily, in a system using such a method, error-correcting coding is performed on the transmitting side while error-correcting decoding is performed on the receiving side.
A convolutional code is particularly advantageous for transmission on a communication path with a low signal power to noise power ratio (S/N ratio). As further explained below, a convolutional code effectively spreads the information contained in each bit of the original message into several bits of the transmitted signal. The receiver determines the value of each original bit from the received signals representing the bits of the transmitted signal. Because the transmitted signal contains redundant information, the original bit values can still be determined with good accuracy even if some of the bit values in the transmitted signal are corrupted by noise in the transmission path. The receiver can use a probabilistic or “soft” decoding scheme. If a most likely path decoding method such as Viterbi decoding is used, soft decision decoding can be performed easily and a high coding gain can be obtained.
In a “punctured” convolutional code, a sequence of bits output from a convolutional encoder is thinned out by deleting some of the bits in accordance with a certain rule. Thus, the redundancy introduced by convolutional encoding is reduced, and a plurality of code rates can be achieved easily.
It is also possible to improve tolerance to noise in a transmission path by diffusing bits of an encoded signal, such as the bits of a code sequence output from a punctured convolutional code encoder, in accordance with a certain rule. “Diffusing” in this context refers to shuffling or reordering the bits.
FIG. 9
shows an example of a transmitter proposed in accordance with the standard DVB-T for DVB ground wave television. This transmitter uses a punctured convolutional code, bit diffusion and a quadrature phase-shift keying (QPSK) system.
In the example shown in
FIG. 9
, serial data output from an information source
1
is input to a convolutional encoder
2
, and mother code sequences X and Y are generated by the encoder
2
. Each of X and Y represents a 1-bit code sequence. Thus, each bit of original data from information source
1
results in generation of two bits of mother code data; one bit in sequence X, and one bit in sequence Y. Stated another way, in this example, the code rate of convolutional encoder
2
is set to 1/2.
FIG. 10
shows an example of the convolutional encoder
2
. The particular encoder
2
is not arranged in accordance with the DVB-T standard; it is a simple encoder intended for explanation of the principle of convolutional processing. In this example, 1-bit serial data output from an information source
1
is input through a terminal
21
, delayed one clock cycle by each of delay circuits
22
and
23
and thereafter output to adder circuits
24
and
25
. The output from terminal
21
and the output from delay circuit
22
are also supplied to the adder circuit
24
. Adder circuit
24
adds these groups of data together (by exclusive OR operation) and outputs the result of this addition as data X through a terminal
26
. Adder circuit
25
adds the output from the terminal
21
and the output from the delay circuit
23
together (by exclusive OR operation) and outputs the result of this addition as data Y through a terminal
27
.
In this example, the two mother code bits X and Y which are obtained when one original bit is input at terminal
21
will depend on the internal state of the delay circuits
22
and
23
prior to arrival of that original bit. The state of the delay circuits
22
and
23
in turn will depend upon the values of the bits which were previously supplied through terminal
21
. Stated another way, the information in each bit of the original message is spread among several bits of the mother code sequences. In this example, the constraint length is 3, the number of internal delay elements is 2, the number of states is 4, and the code rate is 1/2.
FIG. 11
is a state diagram showing state transitions of the convolutional encoder shown in FIG.
10
. If an original code bit with value 0 is input through terminal
21
when the state is 00 (when each of the outputs of the delay elements
22
and
23
is 0), (XY)=(00) is output through the terminals
26
and
27
. That is, mother code bit
0
is output as data X through terminal
26
, whereas mother code bit
0
is output as data Y through terminal
27
. The state is also 00 after the transition resulting from the 0 input; the outputs of each of delay elements
22
and
23
remain 0. In the case where 1 is input when the state is 00, (XY)=(11) is output and the state changes to 10. In the case where 0 is input when the state is 01, (XY)=(11) is output and the state changes to 00. In the case where 1 is input when the state is 01, (XY)=(00) is output and the state changes to 10.
The inputs and outputs associated with these and other states are shown in
FIG. 11
as expressions such as “1/01”, denoting input/outputs. In each such expression, the first digit represents the input, whereas the second digit represents the X output resulting from that input and the last digit represents the Y output resulting from the input.
The mother code sequences X and Y provided by convolutional encoder
2
are input to a bit erase circuit
3
, which performs bit erasing in accordance with a predetermined rule, and forms the remaining bits into a serial bit stream constituting a punctured convolutional code message. The bit erase circuit
3
erases data at predetermined positions in the mother code sequences (XY), in accordance with an erase map:
X: 10
Y: 11
Bits corresponding to 1 in the erase map are transmitted but bits corresponding to 0 in the map are not transmitted (erased). Stated another way, every other bit in the X mother code sequence is omitted from the serial bit stream formed by the bit erase circuit. Thus, if the outputs of convolutional encoder
2
in response to two successive inputs are X
1
, Y
1
in response to the first input and X
2
, Y
2
in response to the next input, the bit erase circuit will transmit a serial stream X
1
Y
1
Y
2
. The same series of operations is repeated during every two successive clock cycles of the apparatus.
The bit erase circuit reduces redundancy in the coded message and thus changes the code rate. Considering the convolutional encoder and the bit erase circuit together, the number of bits in the original message input to the convolutional encoder
2
is 2 and the number of bits in the punctured convolutional code output from the bit erase circuit
3
is 3, so that the code rate is 2/3.
The bit stream or serialized punctured convolutional code sequence output from the bit erase circuit
3
is input to a serial-parallel converter
4
. Serial-parallel converter
4
converts one input data sequence X
1
, Y
1
, Y
2
, . . . into two data sequences (x, y).
The data sequences x and y from converter
4
undergo bit diffusion in
Lerner David Littenberg Krumholz & Mentlik LLP
Luther William
Sony Corporation
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