Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
1999-09-24
2002-05-14
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S101000, C710S071000, C710S052000, C710S060000, C320S118000, C320S118000, C320S118000
Reexamination Certificate
active
06388591
ABSTRACT:
The present invention relates generally to a receiver interface, and particularly to a receiver interface for a non-industry standard bus that is compatible with AT Attachment Packet Interface's Task File.
BACKGROUND OF THE INVENTION
Satisfying the apparently insatiable demand for ever-increasing microprocessor clock rates presents a challenge to designers of Compact Disc Read-Only-Memory (CD-ROM) devices.
FIG. 1
illustrates the cause of this challenge, showing a CD-ROM Device
30
connected to a personal computer (PC)
32
via an Integrated Disc Electronics (IDE) Bus
34
. Consisting of 40 wires, IDE Bus
34
has a maximum clock rate of 66 MHZ and supports up to 32 bits of parallel data. IDE Bus
34
transports single-ended, parallel signals that use Transistor-to-Transistor Logic (TTL) voltage level signaling. In other words, each line, or wire, of IDE Bus
34
carries a single signal that represents a digital “1” via a voltage level of approximately 5 volts and a digital “0” via a voltage level of approximately 0 volts.
AT Attachment (ATA) Interface
36
a
enables PC
32
to support CD-ROM players. ATA Interface
36
a
is coupled to the microprocessor's local bus, a peripheral Component Interconnect (PCI) Bus
40
. The maximum clock rate of IDE Bus
34
is limited by that of PCI
40
; i.e., 66 MHZ. This clock rate is not adequate to enable PC
32
to simultaneously play music and video stored on a CD-ROM. Thus, the demand for speed militates that data transfer rates between CD-ROM player
30
at least equal, if not exceed, the clock rate of PCI
40
.
One solution is to increase the width of the data path between PC
32
and CD-ROM Device
30
, i.e., increasing the number of lines of IDE Bus
34
. A transfer rate of greater than 66 MHZ could be achieved by doubling the number of wires of IDE Bus
34
from 40 to 80; however, such a large pin/wire count is unlikely to gain wide acceptance. Another approach to achieving higher clock and data transfer rates would be to couple CD-ROM Device
30
to Direct Memory Access (DMA) Interface
42
, rather than PCI
40
. Increasing the data transfer rate in this manner comes at the cost of backward compatibility with devices using ATA Interface
36
. Thus, a need exists for an interface that supports data transfer rates greater than that possible with the IDE Bus
34
, is compatible with the ATA Interface and uses no more than the number of wires of IDE Bus
34
.
No technology currently available entirely satisfies this need. IEEE Standard 1394 defines a high speed, isochronous, external bus for personal computers. Sometimes called a “Fire Wire” because of its speed, the 1394 bus is not widely used, despite its speed and flexibility, because of its expense.
AT Attachment Packet Interface (ATAPI) for CD-ROMs is an extension of the ATA Interface that supports connection of CD-ROM players and tape players to personal computers. The ATAPI Standard (SFF-8020i) defines a Task File, a set of registers used by the peripheral devices and personal computer, used to transfer data. According to ATAPI, commands are communicated using packets. Generally described, a packet is a portion of a message, which may include many packets. Typically, each packet includes destination information and data, or a payload. A packet may also include a packet ID (PID) and a cyclical redundancy check (CRC). Because each packet of a message includes a PID, packets need not be transmitted in order to successfully reconstruct the message. Many protocols using packets support isochronous data transfer, as opposed to synchronous data transfer. lsochronous data transfer enables video data to be transmitted as quickly as it is displayed and generally supports very high data transfer rates. However, devices using ATAPI also typically use the IDE Bus, thereby limiting the maximum data transfer rate below the theoretical maximum rate.
Low Voltage Differential Signaling (LVDS) is an alternative to standard signaling, which uses TTL voltage levels and is single-ended. LVDS data transmission is less susceptible to common-mode noise than a single-ended scheme because two wires with opposite current/voltage swings are used instead of a single wire. Because of the reduced noise concerns, low voltage level swings can be used thereby reducing power consumption and allowing faster switching rates. However, merely replacing each single-ended wire of the IDE bus with two LVDS wires is unacceptable because of the increased wire count of the resultant bus as compared to the IDE bus.
SUMMARY OF THE INVENTION
The present invention is a receiver interface compatible with the ATA Interface and the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with the IDE bus by using a serial bus having fewer lines than an IDE Bus. The receiver interface includes a converter, a depacketizing circuit, and an ATAPI receiver circuit. The converter converts a first set of signals from a serial bus into a second set of signals. The first set of signals are serial to one another and use low-voltage, differential signaling (LVDS). The first set of signals are adapted to be received on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) bus. In contrast, the second set of signals are serial to another and use TTL voltage levels and single-ended signaling. Additionally, the second set of signals use a packet format to represent a packet. The depacketizing circuit disassembles the packet represented by the second set of signals to generate a third set of signals, which are parallel to one another and use TTL, single-ended signaling. The third set of signals represents a payload of the packet. The ATAPI receiver circuit stores a fourth set of signals at a location within the ATAPI in response to the third set of signals. The fourth set of signals representing a portion of the payload of the packet.
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patent: 4023144 (1977-05-01), Koening
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 5134702 (1992-07-01), Charych et al.
patent: 5247652 (1993-09-01), Uda
patent: 5485488 (1996-01-01), Van Brunt et al.
patent: 5968147 (1999-10-01), Polfer et al.
patent: 6121906 (2000-09-01), Kim
Jeanpierre Peguy
Mai Lam T.
Oak Technology, Inc.
Pennie & Edmonds LLP
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