Apparatus and method for reading, writing, and refreshing memory

Details Apparatus and method for reading, writing, and refreshing memory Apparatus and method for reading, writing, and refreshing memory

1989-07-03

1994-07-12

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 3642557, 3642563, 3642564, 3649555, 364DIG1, 364DIG2, 365 49, 3652385, G06F 108

Patent

active

053296290

ABSTRACT:
A computer memory system is provided. Received memory requests can be for addresses which are virtual or physical. The type of address is determined, and a virtual/physical bit is set and stored. At least row address bits are compared to one or more registers which contain either a virtual or a physical row address, corresponding to a row addressed by a row address latch. When there is a hit with respect to one of these registers, column address bits are used to select the requested memory element, without the necessity for a virtual-to-physical translation. When there is a miss on all registers, a physical address is obtained, either from the requested address when this is physical, or from a virtual-to-physical translation. The physical address is used to load a new row address into a row address latch. Some column address bits are changed only when there has been a miss. A refresh cycle is described, which includes reading back into a row address latch the same row address which occupied the row address latch before the refresh cycle, thus preserving locality information or structure.

REFERENCES:
patent: 3893084 (1975-07-01), Kotok et al.
patent: 4292674 (1981-09-01), Scheuneman
patent: 4453230 (1984-06-01), Mizoguchi et al.
patent: 4563737 (1986-01-01), Nakamura et al.
patent: 4637024 (1987-01-01), Dixon et al.
patent: 4774653 (1988-09-01), James
patent: 4774659 (1988-09-01), Smith et al.
patent: 4802084 (1989-01-01), Ikegaya et al.
patent: 4803621 (1989-02-01), Kelly
patent: 4920477 (1990-04-01), Colwell et al.
patent: 4961135 (1990-10-01), Uchihori
patent: 4985825 (1991-01-01), Webb, Jr. et al.
patent: 4991081 (1991-02-01), Bosshart
Shankar, Kapil, "Wait-State Remover Improves System Performance," VLSI Systems Design, Nov. 1986, pp. 102-104.
"CHMOS DRAM-A New Memory Alternative For Digital Signal Processing Applications," Intel Memory Components Handbook Supplement, 1985, pp. 1-276-1-279.
"Sun-4/110. The First Supercomputing Desktop Workstation," Electronic Engineering Times, Feb. 8, 1988, p. T35.
Stephen A. Ward and Robert C. Zak, "Static-column RAM as Virtual Cache,".
Stephen A. Ward and Robert C. Zak, "Set-associative Dynamic Random Access Memory".
James R. Goodman and Men-chow Chiang, "The Use of Static Column RAM as a Memory Hierarchy,".

Affiliated with

Also associated with

Rating

Apparatus and method for reading, writing, and refreshing memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for reading, writing, and refreshing memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for reading, writing, and refreshing memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-403819