Excavating
Patent
1991-01-11
1992-07-07
Atkinson, Charles E.
Excavating
365200, 371 36, 371 681, G06F 1100
Patent
active
051289440
ABSTRACT:
An erasable, programmable ROM (10) with three redundant bit-cell arrays (10A, 10B, 10C) includes an error-flagging circuit (30) that detects bit-cell failures and provides notification of each such failure. The error-flagging circuit (30) includes a plurality of XOR gates (32), each receiving the corresponding redundant data bits for one of the bits of an addressed byte, and a NOR gate (36) which receives the outputs from each of the XOR gates (32). Each XOR gate detects when the logic states for the input redundant bits are not identical, indicating a bit-cell failure has occurred, and provides a corresponding logic state output. The NOR gate (36) detects when any of the XOR gates (32) has indicated a bit-cell failure, and generates an error-flag output providing notification of such failure.
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Chang Ki S.
Flaherty Edward H.
Tiernan Mark W.
Atkinson Charles E.
Donaldson Richard L.
Grossman Rene E.
Hollander James F.
Texas Instruments Incorporated
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