Apparatus and method for providing a programmable delay with low

Details Apparatus and method for providing a programmable delay with low Apparatus and method for providing a programmable delay with low

1996-04-03

1998-03-10

Safourek, Benedict V.

Pulse or digital communications

Testing

Phase error or phase jitter

327395, 371 1, H04B 1700

Patent

active

057270210

ABSTRACT:
A printed circuit board tester that compensates for the different propagation length of each channel including a single-input delay cell, at least one multiple-input delay cell, and a multiplexor. The delay cells are connected to one another in a chain. Further, the single-input delay cell is the first delay cell in the chain, and each multiple-input delay cell has the ability to select one of its inputs. A timing signal is applied to each delay cell, and to the multiplexor. The inputs of the multiple-input delay cells are connected to the output of the single-input delay cell, and to the outputs of any preceding multiple-input delay cells in the chain. The single-input delay cell delays the timing signal. Each multiple-input delay cell is programmed by the tester to select one of its inputs; it then delays the selected input. Finally, the multiplexor is programmed by the tester to select either the timing signal or one of the outputs of the delay cells. The signal selected by the multiplexor is the timing signal delayed by an amount necessary to compensate for the propagation length of the channel.

REFERENCES:
patent: 4231104 (1980-10-01), St. Clair
patent: 4637018 (1987-01-01), Flora et al.
patent: 4700347 (1987-10-01), Rettberg et al.
patent: 5274796 (1993-12-01), Conner
patent: 5313501 (1994-05-01), Thacker
patent: 5469477 (1995-11-01), Holmberg
U.S. Patent Application, In re: Muething et al., Ser. No. 08/510,079, Filed: Aug. 1, 1995, For: Low Cost CMOS Tester, Group: 2213.

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