Boots – shoes – and leggings
Patent
1986-01-29
1988-07-05
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 1300
Patent
active
047559365
ABSTRACT:
A cache memory unit is disclosed in which, in response to the application of a write command, the write operation is performed in two system clock cycles. During the first clock cycle, the data signal group is stored in a temporary storage unit while a determination is made if the address signal group associated with the data signal group is present in the cache memory unit. When the address signal group is present, the data signal group is stored in the cache memory unit during the next application of a write command to the cache memory unit. If a read command is applied to the cache memory unit involving the data signal group stored in the temporary storage unit, then this data signal group is transferred to the central processing unit in response to the read command. Instead of performing the storage into the cache memory unit as a result of the next write command, the storage of the data signal in the cache memory unit can occur during any free cycle.
REFERENCES:
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 3896419 (1975-07-01), Lange et al.
patent: 3979726 (1976-09-01), Lange et al.
patent: 4245304 (1981-01-01), Porter et al.
patent: 4264953 (1981-04-01), Douglas et al.
patent: 4332010 (1982-05-01), Messina et al.
patent: 4345309 (1982-08-01), Arulpragasam et al.
patent: 4439829 (1984-03-01), Tsiang
patent: 4486856 (1984-12-01), Heckel et al.
patent: 4573116 (1986-02-01), Ong et al.
patent: 4612612 (1986-09-01), Woffinden et al.
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4682281 (1987-07-01), Woffinden et al.
Blount et al., IBM Tech. Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, pp. 262-263.
Alsing et al., EP A2 0039227 Apr. 27, 1987.
Flahive Barry J.
Keller James B.
Stewart Robert E.
Chun Debra A.
Digital Equipment Corporation
Holloway William W.
Moran Maura K.
Shaw Gareth D.
LandOfFree
Apparatus and method for providing a cache memory unit with a wr does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for providing a cache memory unit with a wr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for providing a cache memory unit with a wr will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2336581