Boots – shoes – and leggings
Patent
1993-01-11
1996-09-24
Chan, Eddie P.
Boots, shoes, and leggings
36446402, 364DIG1, 3642469, 3642466, 365195, 39518503, 39518504, G06F 1214, G06F 1216, G06F 1700
Patent
active
055599923
ABSTRACT:
A data protection apparatus has chip select logic, a protection circuit and one or more memory devices. The chip select logic is designed so that when protected memory is addressed, more than one selection signal is generated. In this way, a protected memory area may encompass all, or a portion, of one or more memory devices. The additional selection signal is processed by a protection circuit which will interrupt the processor if protected memory is addressed during a write cycle in the absence of a request signal which the processor is programmed to generate just prior to its writing to a protected memory area.
REFERENCES:
patent: 3827029 (1974-07-01), Schlotterer et al.
patent: 4141068 (1979-02-01), Mager et al.
patent: 4376299 (1983-03-01), Rivest
patent: 4388695 (1983-06-01), Heinemann
patent: 4566106 (1986-01-01), Check, Jr.
patent: 4644494 (1987-02-01), Muller
patent: 4802117 (1989-01-01), Chrosny et al.
patent: 4805109 (1989-02-01), Kroll et al.
patent: 4875156 (1989-10-01), Tanagawa et al.
"Microsoft Press.RTM. Computer Dictionary"; Microsoft Press, 1991; pp. 19 and 160.
Fl uckiger Daniel
Stutz Peter
Ascom Autelca AG
Bragdon Reginald G.
Chan Eddie P.
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