Apparatus and method for programming voltage protection in a non

Static information storage and retrieval – Floating gate – Particular biasing

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365226, G11C 1604

Patent

active

059432632

ABSTRACT:
A memory system comprising an array of memory cells, a programming voltage node for receiving a first programming voltage, a memory controller which controls memory programming operations on the array of memory cells, and voltage detection circuitry, operably coupled to the memory controller and the programming voltage node, with the voltage detection circuitry being configured to enable the memory controller to initiate one of the programming operations if the first programming voltage exceeds a first voltage level and to continue the programming operation once the programming operation has been initiated if the first programming voltage drops to a second voltage level and to terminate the programming operation once the programming operation has been initiated if the first programming voltage drops below the second voltage level, with the first voltage level being greater than the second voltage level. And a method of controlling the operation of a memory system which comprises an array of memory cells, the method comprising the steps of providing a first programming voltage, initiating a memory programming operation if the first programming voltage magnitude exceeds a first voltage level, continuing the initiated programming operation if the first programming voltage remains greater in magnitude than a second voltage level, with the first voltage level magnitude being greater in magnitude than the second voltage level, and terminating the initiated programming operation if the first programming voltage magnitude drops below the second voltage level.

REFERENCES:
patent: 5003192 (1991-03-01), Beigel
patent: 5109257 (1992-04-01), Kondo
patent: 5199032 (1993-03-01), Sparks et al.
patent: 5274827 (1993-12-01), Haggerty et al.
patent: 5663918 (1997-09-01), Javanifard
Intel Data Book excerpt (pp. 3-157, 3-190 and 3-191) (Admitted prior art under Rule 1.06 (c)).
Yoo, S., et al., "Variable Vcc Design Techniques for Battery-Operated DRAM's", IEICE Transactions on Electronics, No. 5, Tokyo, Japan, pp. 839-843, (May 1993).

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