Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-03-29
2003-12-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290, C365S185180
Reexamination Certificate
active
06657894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a method and an apparatus for programming a virtual ground nonvolatile memory cell array without disturbing adjacent cells.
2. Description of the Related Art
FIG. 3
is a block diagram that illustrates the structure of a prior art nonvolatile memory cell where a nonvolatile memory cell
70
includes an N-channel MOSFET structure. The nonvolatile memory cell
70
includes a P type substrate
706
with two buried N+ junctions, one being the source
700
and the other being the drain
701
. A channel region
707
is formed between the source
700
and the drain
701
. Above the channel is a first isolating layer
703
, which generally is a silicon oxide layer. On top of the first isolating layer
703
is a trapping layer
704
, which generally is a nitride layer. The trapping layer
704
forms the memory retention layer that traps the electrons as they are injected into the nitride layer. A second isolating layer
705
, which generally is an oxide layer, is formed to overlay the silicon nitride layer. The silicon oxide layer
705
electrically isolates a conductive gate
702
formed over the second isolating layer
705
. The two silicon oxide layers
703
and
705
function as isolation dielectric layers.
To program or write the nonvolatile memory cell
70
, voltages are applied to the drain
701
and the gate
702
and the source
700
is grounded. These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source
700
and begin accelerating towards the drain. As they move along the length of the channel, they gain energy. If they gain enough energy they are able to jump over the potential barrier of the isolation layer
703
into the trapping layer
704
and become trapped. The probability of this occurring is at a maximum in the region of the gate next to the drain because it is near the drain where the electrons gain the most energy. The accelerated electrons are termed hot electrons and once injected into the nitride layer they become trapped and remain stored therein.
The continuing demand for higher speed and lower cost semiconductor memories has led to the development of the virtual ground memory design for programmable nonvolatile memories. A virtual ground memory design can increase array density while maintaining process compatibility with existing semiconductor processes.
While virtual ground memory designs enjoy advantages from increased bit density, they have a number of disadvantages. One disadvantage is the problem of unwanted interaction between adjacent memory cells. This interference can take the form of a program disturb condition, in which programming of a selected cell leads to unwanted programming of unselected adjacent memory cells. This interference can also take the form of read access degradation due to an unwanted current component. In both situations, the interference affects memory cells located in adjacent columns and connected to the selected row line. Interaction between adjacent cells also causes parasitic currents that interfere with reading, erasing and programming of individual cells. Ultimately, the access speed and integrity of the memory array is adversely affected by these problems.
To avoid the disturbance to adjacent cells, some isolation spaces are formed to isolate a plurality of connecting cells, as illustrated in
FIGS. 1 and 2
. However, these conventional designs are space-wasting and inefficient. Such designs will lead to a significant overall size increment in a semiconductor memory chip so as to prohibitively increase the occupied space and cost.
Thus, there is a general need in the art for an optimal programming mechanism for virtual ground nonvolatile memory arrays, and more particularly, for a programming that allows for programming of a selected memory cell without disturbing data stored on adjacent unselected memory cells.
SUMMARY OF THE INVENTION
The present invention advantageously provides a method and an apparatus for programming a selected cell within a virtual ground nonvolatile memory cell array without disturbing adjacent array cells.
A virtual ground nonvolatile memory cell array according to a preferred embodiment of the invention is formed by a plurality of adjacent nonvolatile memory cells arranged in rows and columns so as to form an array. The nonvolatile memory cells are formed by an N channel MOSFET where each cell includes a gate, a source, a drain and a channel between the source and the drain. A trapping layer is provided between two isolating layers. The trapping layer stores an amount of electrons in the erase state for the memory cells according to the invention.
The invention further provides a method for programming a selected memory cell that substantially avoids the disturbance of data stored in adjacent cells. As a part of electrically programmable semiconductor memory device, an array of nonvolatile memory cells arranged in rows and columns so as to form an array. The nonvolatile memory cell array according to a preferred embodiment of the invention includes a control gate, a first terminal and second terminal, the control gates of memory cells in a row being coupled to the same wordline. According to this particular embodiment, the method according to the invention comprises the steps of applying a first potential to a, first bitline coupled to a source of the selected nonvolatile memory cell, applying a second potential to a second bitline coupled to a drain of the selected nonvolatile memory cell, and applying a third potential to a first wordline coupled to a gate of the selected memory cell.
To avoid disturbance between the memory cells in the array, the difference of the first potential and the third potential is sufficient to cause holes to be injected from the source of the selected nonvolatile memory cell to the gate of the selected nonvolatile memory cell. Moreover, the potential difference of the second potential and the third potential is sufficient to cause holes not to be injected from the drain of the selected nonvolatile memory cell to the gate of the selected nonvolatile memory cell. A bit is programmed to the trapping layer of the selected nonvolatile memory cell at a side near the source of the selected nonvolatile memory cell.
In addition, to avoid disturbance, a fourth potential can further be applied to a third bitline next to the second bitline. A potential difference of the second and fourth potentials will cause the holes not to be injected to a trapping layer of a nonvolatile memory cell coupled to the third bitline and next to the selected nonvolatile memory cell, where the first, second and fourth potentials are formed as a first potential set.
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Lu Tao-Cheng
Tsai Wen-Jer
Yeh Chih-Chieh
Baker & McKenzie
Hoang Huan
Macronix International Co. Ltd
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