Apparatus and method for producing an output signal from a memor

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Accelerating switching

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Details

327398, 327112, 327288, 326 56, 326 57, H03K 1900

Patent

active

055572294

ABSTRACT:
An output device and method of operating it are disclosed. The output device includes a output control unit and an output buffer unit. The output control unit produces a data release (INR) signal after producing an output release (OR) signal, for example, by delaying the OR signal. The INR signal causes release of an output signal from a sense amplifier, resulting in a data signal. The output buffer includes n- and p-channel switching transistors and control units controlling their gates. In response to activation of the OR signal, the control units bring the voltage of the gates of the switching transistors to respectively slightly above and slightly below the threshold levels of their gates. In response to the data signal, the control units fully activate one of the switching transistors and deactivate the other of the switching transistors depending on the voltage level of the data signal. The speed with which the control units respond to the data signal is controlled.

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patent: 5087840 (1992-02-01), Davies et al.
patent: 5173627 (1992-12-01), Lien
patent: 5293082 (1994-03-01), Bathaee
patent: 5414379 (1995-05-01), Kwon
M. Ando, et al., "A 0.1-.mu.A Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, pp. 1708-1710.
T. Wada, et al., "Simple Noise Model and Low Noise Data-Output Buffer for Ultrahigh-Speed Memories", IEEE Journal of Solid-State Circuits, vol. 25, No. 6., Dec. 1990, pp. 1586-1588.

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