Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-08-10
2003-05-13
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S699000, C345S213000, C345S099000, C348S521000
Reexamination Certificate
active
06563484
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a monitor, and more particularly, to an apparatus and method for processing a synchronizing signal of a monitor.
2. Background of the Related Art
Generally, a monitor is an apparatus for displaying an image signal of an image mode such as SVGA (800×600), XGA (1024×768) and SXGA (1280×1024). The image signal is transmitted from a main body connected to a monitor, for example, a video card of a work station or a personal computer, after a series of signal processing. Examples of flat panel display devices include monitors which employ a cathode ray tube, and a digital monitor which employs a liquid crystal display (LCD). Particularly, as a typical flat panel display device, the digital monitor suitable for high definition has been commercially used.
As shown in
FIG. 1
, a related art apparatus for processing a synchronizing signal of a monitor includes a synchronizing signal processor
1
, a microcomputer
2
, a phase locked loop (PLL)
3
, and a scaler
4
.
When various synchronizing signals adapted to standards of respective system makers, such as a sync on green (SOG) signal and a complex synchronizing signal C-sync, are input to the synchronizing signal processor
1
, the synchronizing signal processor
1
separates these signals and outputs the complex synchronizing signal C-sync and a vertical synchronizing signal V-sync. On the other hand, when a horizontal synchronizing signal H-sync and the vertical synchronizing signal V-sync are input to the synchronizing signal processor
1
, the synchronizing signal processor
1
passes these signals straight through.
The microcomputer
2
determines whether the monitor should be in an image mode or a display power management (DPM) mode, in accordance with the frequency of the synchronizing signals output from the synchronizing signal processor
1
. The microprocessor
2
then outputs a control signal to perform a signal processing operation according to a corresponding image mode.
The PLL
3
generates a clock pulse according to the control signal of the microcomputer
2
and also generates a new horizontal synchronizing signal synchronized with the clock pulse. The scaler
4
processes R/G/B image signals for each unit of frame in accordance with the clock pulse and the horizontal synchronizing signal from the PLL
3
.
If no vertical or horizontal synchronizing signals are detected, it is determined that the monitor is not used. This indicates that the monitor should be in DPM mode. In that case, the microcomputer
2
supplies power only to essential elements for standby state and cuts off the power for the other elements, such as a deflection IC and a heater which require high power.
In operation, the synchronizing signal processor
1
receives either the SOG signal and the complex synchronizing signal C-sync or the horizontal synchronizing signal Hsync and the vertical synchronizing signal V-sync from a main body. If the SOG signal is input to the synchronizing signal processor
1
, as shown in
FIG. 2
a,
the synchronizing signal processor
1
processes the SOG signal so that a signal below a synchronizing signal detecting level is output at high level, and a signal above the synchronizing signal detecting level is output at low. Thus, the synchronizing signal processor
1
finally outputs a complex synchronizing signal and a vertical synchronizing signal.
Furthermore, the synchronizing signal processor outputs the horizontal synchronizing signal and the vertical synchronizing signal, i.e., separate synchronizing signals, without additional processing. The synchronizing signal processor divides the complex synchronizing signal into the horizontal synchronizing signal and the vertical synchronizing signal and outputs them to the microcomputer
2
.
Subsequently, the microcomputer
2
identifies the proper mode of the monitor, i.e., image mode or DPM mode, in accordance with the frequency of the synchronizing signals output from the synchronizing signal processor
1
. The microcomputer
2
then outputs a control signal to the PLL
3
to supply a corresponding sampling clock to the scaler
4
.
The PLL
3
generates a clock pulse set by the control signal of the microcomputer
2
with a horizontal synchronizing signal synchronized with the clock pulse, and supplies the clock pulse and the horizontal synchronizing signal to the scaler
4
. The scaler
4
processes R/G/B image signals transmitted from the main body in accordance with the control signal of the microcomputer
2
.
In normal operation, when the monitor is not used, no synchronizing signal is input to the synchronizing signal processor
1
. Accordingly, the microcomputer
2
proceeds to the DPM mode.
However, since a G signal exists even if no synchronizing signal is input to the synchronizing signal processor, the G signal is input to the synchronizing signal processor through the SOG input terminal. As shown in
FIG. 2
b,
when the synchronizing signal is abnormally separated from the G signal, the abnormal synchronizing signal is input to the microcomputer
2
. Accordingly, although the monitor is not operating, the microcomputer
2
does not proceed to the DPM mode. As a result, an image processing error may occur. This could lead to poor picture quality and unnecessary power consumption.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide an apparatus and method for processing a synchronizing signal of a monitor that substantially obviates at least one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide an apparatus and method to detect an abnormal synchronizing signal.
Another object of this invention is to avoid poor picture quality and errors in proceeding to a DPM mode in a monitor.
Another object of this invention is to prevent unnecessary power consumption in a monitor.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an apparatus for processing a synchronizing signal of a monitor according to a preferred embodiment of the present invention includes a synchronizing signal processor for separating a synchronizing signal from SOG signal, a detector for detecting a synchronizing signal width and a horizontal line width output from the synchronizing signal processor, a microcomputer for determining abnormality of the synchronizing signal using relative ratio of the detected synchronizing signal width and horizontal line width, and a clock generator for generating a clock in accordance with a control signal of the microcomputer and outputting the clock to the detector.
In order to achieve the at least above objects in whole or in parts, there is further provided a method for processing a synchronizing signal of a monitor according to the present invention, including detecting a synchronizing signal width and a corresponding horizontal line width, comparing ratio of the synchronizing signal width to the horizontal line width with a set ratio, and determining abnormality of the synchronizing.
In order to achieve the at least above objects in whole or in parts, there is further provided an apparatus for processing a synchronizing signal of a monitor that includes a synchronizing signal processor to separate a synchronizing signal from an input signal, a detector to detect a synchronizing signal width and a horizontal line width based on the synchronizing signal, a microcomputer to determine whether the synchronizing signal is normal or abnormal, in accordance with a relative ratio of the synchronizing signal width and the horizontal line width, and
Fleshner & Kim LLP
LG Electronics Inc.
Nguyen Hau
LandOfFree
Apparatus and method for processing synchronizing signal of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for processing synchronizing signal of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for processing synchronizing signal of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3075536