Apparatus and method for processing data with a plurality of fla

Details Apparatus and method for processing data with a plurality of fla Apparatus and method for processing data with a plurality of fla

1994-05-19

1999-11-23

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

712 43, 712210, 708601, G06F 930

Patent

active

059918683

ABSTRACT:
In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having different widths, based on the operated results. Selectors select a predetermined flag group in accordance with the direction of a conditional branch instruction. A branch judging unit judges whether a branch is taken or not by referring to the selected flag group.

REFERENCES:
patent: 4788655 (1988-11-01), Nakayama et al.
patent: 4811266 (1989-03-01), Woods et al.
patent: 4812971 (1989-03-01), Batts, Jr. et al.
patent: 5034879 (1991-07-01), Woodward et al.
patent: 5151993 (1992-09-01), Yamahata
IBM, "Multiple Queued Condition Codes", IBM Technical Disclosure Bulletin, Jul. 31, (1988), No. 2, pp. 294-296.
"16-bit microprocessor 8086 family".
"Multiple Queued Condition Codes", IBM Technical Disclosure Bulletin, Jul. 31 (1988), No. 2, Armonk, New York, USA.

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