Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
1998-05-27
2001-08-28
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S004000
Reexamination Certificate
active
06282634
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems having vector and scalar data processing registers.
2. Description of the Prior Art
A data processing instruction typically includes within it an opcode portion and one or more register specifying fields. In some systems a register may be treated as a vector register or a scalar register. A vector register specifies a sequence of registers each storing its own data value which is separately operated upon as the data processing instruction repeats its operation upon each data value in the sequence. Conversely a scalar register is a single register storing a single value that operates independently of other registers.
Data processing instructions using, vector registers have a number of advantages over purely scalar operations. The instruction bandwidth required may be reduced since only a single data processing instruction is required to specify a plurality of similar data processing operations to be performed (common in DSP functions such as FIR filters). In the case of a single-issue machine (i.e. one instruction is fetched and decoded each cycle), which is desirable because of its simplicity, higher performance can be achieved with multiple functional units that execute in parallel on different vector instructions.
FIGS. 16 and 17
of the accompanying drawings respectively illustrate a Cray 1 processor register bank and, a Digital Equipment Corporation MultiTitan processor register bank. Both of these prior art processors provide vector and scalar registers.
In the case of the Cray 1, separate vector and scalar register banks
10
,
12
are provided. A 16-bit instruction provides individual opcodes that correspond to different combinations of the registers specified in the instructions being treated as vectors or scalars. This has the disadvantage that an increased number of opcodes need to the provided to represent these various combinations. Furthermore, as the scalar and vector registers are provided in separate register banks
10
,
12
, the opcode needs to be at least partially decoded in order to determined which of the register banks
10
,
12
is to be used for a particular register specified. This additional decode requirement imposes difficulties in being able to read the data values stored in the registers as early as possible.
The Cray 1 processor uses 3-bit register specifying fields R
1
, R
2
, R
3
allowing 8 scalar registers and 8 vector registers to be addressed. In practice, each vector register comprises a stack of registers that can each store a different data value and be accessed in turn in dependence upon a vector length value stored within a length register
16
and mask bits stored within a mask register
18
. However, the limitation of only 8 scalar registers being allowed by the 3-bit register fields is a significant disadvantage for modem compilers that are able to produce faster code if able to target a higher number registers.
The MultiTitan processor provides a single register bank
20
in which each register may operate as a scalar or as part of a vector register. The MultiTitan processor uses a 32-bit instruction to specify its data processing operations. This large amount of instruction bit space allows the instructions themselves to include fields VS
2
, VS
3
that specify whether the registers are vectors or scalars and to include the length of the vectors (Len). Whilst this approach allows a great deal of flexibility, it suffers from the disadvantage that in many circumstances sufficient instruction bit space is not available to enable vector/scalars fields to be included within the instruction without limiting the opcode space available to allow provision of a rich instruction set. Furthermore, the provision of the vector length within the instruction itself makes it difficult to make global changes to the vector length without having to resort to self-modifying code. The MultiTitan technique also rather inefficiently uses its instruction bit space as it devotes equal instruction bit space resources to combinations of vector and scalar registers that are in practice very unlikely to be used (e.g. V=S op S; a sequence of vector registers is filled with the results of an operation performed upon two scalar registers).
SUMMARY OF THE INVENTION
It is an object of the present invention to address at least some of the limitations of the above-described systems.
Viewed from one aspect the present invention provides n apparatus for processing data, said apparatus comprising:
a register bank having a plurality of registers; and
an instruction decoder for decoding data processing instructions, at least one of said data processing instructions having at least an operation specifying code specifying an operation for execution and a first register specifying field specifying a first register within said register bank; wherein
said instruction decoder executes an operation using a given register as either a scalar register or a vector register, execution with said given register being a scalar register comprising executing said operation once upon an operand stored in said given register and execution with said given register being a vector register comprising executing said operation a plurality of times upon operands stored within a predetermined sequence of registers of said register bank selected in dependence upon a register specifying field for said given register; and
said instruction decoder being responsive to said first register specifying field and independent of said operation specifying code to determine whether said operation is to be executed using said first register as either a vector register or a scalar register.
The invention recognises that the register field itself may be made to indicate whether that register is to be treated as a vector or a scalar. Thus, no decode need be performed upon the opcode allowing the register to be accessed early based upon the register field alone and with both the scalar and vector registers being provided together within a single register bank, thus allowing greater flexibility in their use. Furthermore, using the register specifying field to encode whether the register is a scalar or a vector frees instruction bit space for other uses. In practice the technique of the invention provides an advantageously efficient instruction encoding that in turn allows instruction bit space to be made available to enable a larger register bank to be addressed.
In preferred embodiments of the invention, said at least one of said data processing instructions has a second register specifying field specifying a second register;
said instruction decoder executes said operation using said second register as either a scalar register or a vector register; and
said instruction decoder is responsive to said first register specifying field to determine whether said operation is to be executed using said second register as either a vector register or a scalar register.
Such preferred embodiments establish and exploit a correlation in whether the first register is a vector or a scalar and whether the second register is a vector or a scalar. In practice it has been found that some combinations are often used and some are not often used. This may be exploited by supporting the often used combinations and encoding them with the first register field value thereby avoiding having to separately encode the nature of the second register. When the uncommon combination is actually required, this can be accommodated using additional instructions. The unlikely combinations are sufficiently rare that the gains in not having to encode the nature of the second register for every instruction far outweigh the occasional need to provide extra instructions to specify a desired uncommon manipulation.
Whilst it is possible that in some embodiments the correlation may be that when the first register is a scalar the second register is a vector, it has been found
Hinds Christopher Neal
Jaggar David Vivian
Matheny David Terrence
Seal David James
ARM Limited
Niebling John F.
Nixon & Vanderhye P.C.
Whitmore Stacy
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