Apparatus and method for preventing I/O bandwidth limitations in

Details Apparatus and method for preventing I/O bandwidth limitations in Apparatus and method for preventing I/O bandwidth limitations in

1993-03-08

1994-05-17

Smith, Jerry

Boots, shoes, and leggings

G06F 1500

Patent

active

053134133

ABSTRACT:
A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.

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patent: 4977533 (1990-12-01), Miyabayashi
patent: 5042000 (1991-08-01), Baldwin
patent: 5109524 (1992-04-01), Wagner et al.

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