Apparatus and method for preventing bus contention during power-

Details Apparatus and method for preventing bus contention during power- Apparatus and method for preventing bus contention during power-

1995-01-25

1996-09-24

Zarabian, A.

Static information storage and retrieval

Addressing

Counting

36518905, G11C 800

Patent

active

055597530

ABSTRACT:
A DRAM circuit is disclosed with circuitry for disabling data output drivers to prevent bus contention during system power-up. The circuitry includes a counter for counting RAS (or CAS) signals, and for disabling the output data drivers until 7 RAS (or CAS) signals are counted. The output of the counter (called Keep Off) connects to each of the tri-state buffer output drivers, through an AND gate. Other inputs to the AND gate may include an output signal Pwrup from a voltage detection circuit, and other enable signals. The counter uses the RAS signals as a clock signal to three D flip-flops. The Pwrup signal also is used as a reset to each of the flip-flops. The Q output of the flip-flops are anded together, to produce a signal which is released when the count reaches 111.

REFERENCES:
patent: 5311483 (1994-05-01), Takasugi
patent: 5343439 (1994-08-01), Hoshino
patent: 5362996 (1994-11-01), Yizraeli
Micron Technology, Inc., DRAM Data Book, 1992, pp. 1-79.

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