Boots – shoes – and leggings
Patent
1984-12-24
1988-09-27
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1208, G06F 1212
Patent
active
047746548
ABSTRACT:
A prefetching mechanism for a memory hierarchy which includes at least two levels of storage, with L1 being a high-speed low-capacity memory, and L2 being a low-speed high-capacity memory, with the units of L2 and L1 being blocks and sub-blocks respectively, with each block containing several sub-blocks in consecutive addresses. Each sub-block is provided an additional bit, called a r-bit, which indicates that the sub-block has been previously stored in L1 when the bit is 1, and has not been previously stored in L1 when the bit is 0. Initially when a block is loaded into L2 each of the r-bits in the sub-block are set to 0. When a sub-block is transferred from L1 to L2, its r-bit is then set to 1 in the L2 block, to indicate its previous storage in L1. When the CPU references a given sub-block which is not present in L1, and has to be fetched from L2 to L1, the remaining sub-blocks in this block having r-bits set to 1 are prefetched to L1. This prefetching of the other sub-blocks having r-bits set to 1 results in a more efficient utilization of the L1 storage capacity and results in a highter hit ratio.
REFERENCES:
patent: 3928857 (1975-12-01), Carter
patent: 4370710 (1983-01-01), Kroft
patent: 4437155 (1984-03-01), Sawyer et al.
patent: 4464712 (1984-08-01), Fletcher
patent: 4490782 (1984-12-01), Dixon et al.
patent: 4533995 (1985-08-01), Christian et al.
Pomerene James H.
Puzak Thomas R.
Rechtschaffen Rudolph N.
So Kimming
Arnold Jack M.
International Business Machines - Corporation
Lee Thomas C.
Zache Raulfe B.
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