Apparatus and method for prefetching data to load buffers in a b

Multiplex communications – Wide area network – Packet switching

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395872, 395308, 370402, G06F 1300

Patent

active

056641176

ABSTRACT:
A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the requested data from the first bus and prefetches one or more additional data segments stored in memory locations sequentially following the memory location storing the requested data. The prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests. Supply circuitry transfers each data segment from the buffer to the second bus in response to receiving an address corresponding to the particular data segment on the address input circuitry.

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