Boots – shoes – and leggings
Patent
1996-02-22
1998-02-03
Swann, Tod R.
Boots, shoes, and leggings
39542103, 395403, 364DIG1, G06F 1200
Patent
active
057154252
ABSTRACT:
A central processing unit is connected to an external memory including system memory and an external cache. The central processing unit includes a First-In-First-Out (FIFO) load buffer configured to generate an access to the external memory in response to a data prefetch command. The access to external memory has an associated data load latency period as data is moved from the system memory into the external cache. Instead of requiring the access to external memory to be completed before another FIFO load buffer address is processed, as is typically required in a FIFO load buffer configuration, the FIFO load buffer responds to the data prefetch command by processing additional stored addresses during the data load latency period.
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Goldman Gary S.
Greenley Dale R.
Petrick Bruce E.
Tremblay Marc
Galliani William S.
Langjahr David
Sun Microsystems Inc.
Swann Tod R.
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