Electrical computers and digital processing systems: processing – Processing architecture
Patent
1997-12-12
2000-05-09
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
712206, 712208, 712209, 710 1, G06F 1300
Patent
active
060617756
ABSTRACT:
A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. To expedite the dispatch of instructions, when a cache line is scanned, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the microcode pointer and the functional bits of the predecode data to multiplex instruction specific bytes of the first microcode instruction to the MROM unit. If the predicted first microcode instruction is not the actual first microcode instruction, then in a subsequent clock cycle, the actual microcode instruction is dispatched the MROM unit and the incorrectly predicted microcode instruction is canceled.
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Calle Mauricio
Southard Shane
Tran Thang M.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Ciccozzi John
Kivlin B. Noel
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