Apparatus and method for PLL with equalizing pulse removal

Details Apparatus and method for PLL with equalizing pulse removal Apparatus and method for PLL with equalizing pulse removal

2006-02-14

2006-02-14

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000

Reexamination Certificate

active

06998886

ABSTRACT:
A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circuit. The gate signal leads the feedback signal by approximately one-fourth of a period. Also, an equalizing pulse removal logic circuit is arranged to provide a sync gate signal from the feedback signal, the gate signal, and a sync signal. The sync gate signal is provided such that, if the sync signal includes equalizing pulses, the sync gate signal corresponds to an inactive logic level during the equalizing pulses. A phase-frequency detector of the phase-locked loop circuit is gated such that the phase-frequency detector is not changed by the sync signal if the sync gate signal corresponds to the inactive logic level.

REFERENCES:
patent: 4364091 (1982-12-01), Taguchi et al.
patent: 6483361 (2002-11-01), Chiu
patent: 6642747 (2003-11-01), Chiu
National Semiconductor Corporation, “Video Sync Separator”, LM1881, LM1881-X, Jun. 2003, pp. 1-12.

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