Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2000-05-31
2004-05-04
Vo, Tung T. (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240260
Reexamination Certificate
active
06731686
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to decoding hybrid motion-compensated and transform coded video signals. More particularly, this invention relates to a technique for pipelining variable length decode and inverse quantization operations in a hybrid motion-compensated and transform coded video decoder.
BACKGROUND OF THE INVENTION
Many video applications utilize data compression. More particularly, many video applications utilize transform code compressed domain formats, which include the Discrete Cosine Transform (DCT) format, the interframe predictive code format, such as the Motion Compensation (MC) algorithm, and hybrid compressed formats. The combination of Motion Compensation and Discrete Cosine Transform (MC-DCT) is used in a number of standards, including: MPEG-1, MPEG-2, MPEG-4, H.261, and H.263. The present invention is applicable to any hybrid motion-compensated and transform coded video stream, including MC-DCT.
FIG. 1
illustrates a prior art hybrid motion-compensated and transform coded video decoder
100
. The video decoder
100
includes a buffer
120
which delivers an input video stream to a high level parser
122
, which extracts the motion related information and sends it to the Motion Compensated (MC) Predictor
128
. The MC Predictor
128
also receives a previous picture frame from the previous picture buffer
130
. The MC Predictor
128
uses known techniques to combine the previous picture frame with the motion related information to produce a current picture frame.
The high level parser
122
also applies its output to a Variable Length Decoder (VLD)
124
, which produces quantized coefficients. The Inverse Quantizer (IQ)
126
takes its input from the VLD
124
to produce DCT coefficients, from which the Inverse Discrete Cosine Transform (IDCT) block
132
creates a displaced frame difference signal. An adder
134
is used to add the displaced frame difference signal and the output of the MC predictor
128
to produce a decoded video stream.
The variable length decoder
124
and the inverse quantizer
126
produce a processing bottleneck in prior art decoders. About 85 to 95 percent of the bits in a typical MPEG-2 bitstream represent the variable length code for quantized DCT coefficients. For high bitrate streams such as in DVD, or SDTV/HDTV broadcasts, the efficiency of the variable length decoder becomes crucial. In the case of HDTV, the inverse quantization rate is also relatively high since the picture resolution is high.
The design of efficient variable length decoders has been an active area of research. Inverse quantizers can usually be designed in a straightforward way, but are required to operate at the video pixel rates with additional checks for sparseness of the DCT coefficient blocks. The quantized DCT blocks are in general sparse (that is how the compression efficiency is achieved).
In view of the foregoing, it would be highly desirable to provide an improved technique for variable length decoding and inverse quantization in hybrid motion-compensated and transform coded video decoders. Ideally, the technique would facilitate at least some parallel decoding operations within the serial decoding process so the technique could be effectively implemented in software and in general purpose microprocessors.
SUMMARY OF THE INVENTION
The invention includes a method of pipelining variable length decode and inverse quantization operations in a hybrid motion-compensated and transform coded video decoder. The method includes the step of mapping a new code word to a look-up table to retrieve a code word length, a zero-run length, and a quantized level. A new linear, zig-zagged position of a current coefficient is identified from the zero-run length and a previous zero-run length. The code word length is added to a current bitstream position to yield a new bitstream position. A quantization matrix coefficient from the new linear, zig-zagged position of the current coefficient is selected. The quantized level is multiplied by a predetermined value to produce a quantization product. In the case of inter block processing, a quantized level sign value is added to the quantization product. In the case of intra block processing, the quantization product does not include the quantization level sign. The quantization product is multiplied by a quantization matrix coefficient to form a derived quantization value. The derived quantization value is divided by a predetermined word length to produce a final quantization value. The new linear, zig-zagged position of the current coefficient is converted to a two-dimensional display position. The final quantization value is written at the display position.
The invention also includes an apparatus to pipeline variable length decode and inverse quantization operations in a hybrid motion-compensated and transform coded video decoder. The apparatus includes a counter to identify a leading zero count in a variable length code. A multiplexer with multiplexer input nodes is configured to receive buffered look-up table segments and select nodes to receive the leading zero count. The multiplexer generates a multiplexer output signal. An adder adds the multiplexer output signal and an offset signal to yield a look-up table address. A look-up table returns a level signal, a length signal, and a run signal corresponding to the look-up table address.
The invention provides an improved technique for variable length decoding and inverse quantization in hybrid motion-compensated and transform coded video decoders. The technique facilitates parallel decoding within a serial processing stream. The reformulation of the decoding process through parallel processing facilitates the implementation of the invention in software and in general purpose microprocessors.
REFERENCES:
patent: 5367629 (1994-11-01), Chu et al.
patent: 5452104 (1995-09-01), Lee
patent: 6298087 (2001-10-01), Luna et al.
Gulati Amit
Sriram Parthasarathy
Sudharsanan Subramania I.
Sun Microsystems Inc.
Vo Tung T.
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