Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1998-03-03
2001-06-19
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S354000, C375S373000, C375S325000, C375S326000
Reexamination Certificate
active
06249557
ABSTRACT:
BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION
This invention relates in general to a timing recovery system and method, and more particularly to a phase-locked loop timing recovery system and method which is highly effective in eliminating re-activation. 2. Description of Related Art
At a receiver in a typical communication system, an analog-to-digital converter is utilized to convert a received continuous-time signal into a discrete-time format. One problem which is encountered in this type of system is that the local receiver clock and the remote transmitter clock are asynchronous. If the receiver clock is slower than the transmitter clock, after a long enough period of time, one sample of the received continuous-time signal will be lost. On the other hand, if the local receiver clock is faster than the remote transmitter clock, after a long enough period of time, an extra sample of the received continuous-time signal will be obtained. Thus, the problem of recovering the clock signal is an important problem in many communication systems.
Recently, several high speed digital data services have become commercially available. These high speed digital data services are known as the ISDN(Integral Services Digital Network) basic rate, HDSL(High Speed Digital Subscriber Loop), HDSL2(High Speed Digital Subscriber Loop 2), ADSL(Asymmetric Digital Subscriber Loop), and Tl services.
In these transmission system, the transceiver needs to recover the clock signal to provide the high speed services. In particular, a phase-locked loop (PLL) is need to obtain the clock signal. At the slave side(normally called Remote side, RT), the loop timing needed to be acquired from the received signal sent from the master side(normally called Central Office side, CO). The RT transmitter sends back a signal to the CO side with the synchronous time base acquired in its receiver phase-locked loop. Further, some systems use the signal carrierless AM/PM (CAP) or quadrature amplitude modulation (QAM) signal as the line code, which is very effective when the cable loss is heavily distorted due to skin effect of the cable and the open-ended stub, bridged taps.
One prior phase-locked loop method
100
is illustrated in FIG.
1
. In
FIG. 1
, an input signal
110
is sampled according to a clock signal
112
and input to an analog-to-digital converter
114
. The digital output of the analog-to-digital converter
114
is passed through the feed-forward equalizer
120
and the decision feedback equalizer
122
to produce the output data
124
. To recover the clock signal
112
, the input is sampled and rectified by the rectifier
130
. Then the rectified signal is passed through a high Q bandpass filter
140
. The output of the bandpass filter
140
is then passed to a comparator
150
for determining the clock signal based upon, for example, a comparison of the output of the bandpass filter and a threshold signal.
The phase-locked loop circuit
100
in
FIG. 1
needs a high-Q bandpass filter
140
to extract the carrier component of the input signal
110
. However, this method is not practical to implement with CMOS circuitry, since highly accurate LC components
160
that are needed to achieve the high Q bandpass filter
140
can not be accurately controlled by the current CMOS technology. Hence, such a system
100
needs expensive external components.
Yet another prior method
200
is illustrated in FIG.
2
. The phase-locked loop circuit
200
illustrated in
FIG. 2
shows the sampling of an input signal
210
according to a derived clock signal
212
, which is then provided to an analog-to-digital converter
214
. The digital output of the analog-to-digital converter is passed through the fractionally spaced feed-forward equalizer
220
and the decision feedback equalizer
224
to produce the output data.
The output of the fractionally spaced feed-forward equalizer
220
provides an input to the phase-locked loop
230
. From the output of the fractionally spaced feed-forward equalizer
224
, the phase is determined by a phase detector
232
which is then passed through a loop filter
234
. The loop filter
234
controls a voltage-controlled oscillator
236
to generate the clock signal
212
.
However, the fractionally spaced feed-forward equalizer
220
tends to adjust phase error by itself, i.e., the fractionally spaced feed-forward equalizer
220
only needs the frequency adjustment. However, the phase-locked loop
230
also tries to detect and adjust for phase error. Therefore, this dual phase error compensation via the two paths fight each other and do not converge. Thus, this method requires re-acquisition because of the meta-stability caused by the mutual interaction between phase-locked loop
230
and the feed-forward equalizer
224
.
Regarding this meta-stability, the feed-forward equalizer
224
has to be a fractionally spaced feed forward equalizer (FFE) to achieve high transmission quality of the bit error rate performance under the hash cable environment described above. The fractional spaced feed forward equalizer is basically finite impulse response (FIR) filter. Since, the FIR filter is fractionally spaced, i.e., the input is sampled N times faster than the symbol speed and fed to the FIR which has the unit delay of Tsymbol/N, where Tsymbol is the symbol period, the timing is self-adjusted. Therefore, it is not easy to extract correct timing information from the equalizer parameters.
It can been seen, then, that there is a need for an effective technique to acquire timing in digital data network.
It can be seen that there is a need for a phase-locked loop and method that is implemented using current CMOS circuit technology and which is highly effective in eliminating re-activation.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a phase-locked loop timing recovery system and method which is highly effective in eliminating re-activation.
The present invention solves the above-described problems by providing a timing recovery circuit that prevents phase error over-compensation.
A system in accordance with the principles of the present invention includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal.
Other embodiments of a system in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention is that the timing recovery circuit includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal.
Another aspect of the present invention is that the phase scanner compares the tap coefficients to generate a signal for preventing phase over-compensation by the feed-forward equalizer.
Another aspect of the present invention is that the timing recovery circuit further includes a phase detector for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal.
Another aspect of the present invention is that the signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.
Yet another aspect of the present invention is that the feed-forward equalizer is a fractionally spaced feed-forward equalizer.
Another aspect of the present invention is that the phase scanner further includes a comparator for comparing two taps from the feed-forward equalizer to generate a comparator output signal indicating whether over-compensation by the feed-forward equalizer has occurred, the comparator output signal being mixed with a scan phase signal to generate the signal for preventing phase over-compensation by the feed-forward equalize
Camagna John R.
Gattani Amit
Ling Stanley K.
Takatori Hiroshi
Chin Stephen
Level One Communications Inc.
Liu Shuwang
Merchant & Gould P.C.
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