Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-12-16
2001-03-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S230030
Reexamination Certificate
active
06201760
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a double data rate (DDR) synchronous dynamic random access memory (SDRAM); and, more particularly, to an apparatus and method for performing a data read operation in the DDR SDRAM.
DESCRIPTION OF THE PRIOR ART
Generally, a conventional synchronous dynamic random access memory (SDRAM) synchronized with an external system clock has been employed to improve the operation speed of a dynamic random access memory (DRAM). Up to date, in order to further improve the operation speed, a concept of a double data rate (DDR) synchronous dynamic random access memory (SDRAM) has been suggested. A conventional SDRAM employs only a rising edge of a clock, while the DDR SDRAM employs both rising and falling edges of the clock.
However, a conventional apparatus for performing a data read operation used in the DRAM or SDRAM does not execute a data read operation based on the both edges in the DDR SDRAM. Therefore, it is strongly needed that an apparatus for performing a data read operation in a DDR SDRAM, which is capable of issuing data at both rising and falling edges of the clock.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus for performing a data read operation in a DDR SDRAM that is capable of efficiently issuing two data within one clock by using two-bit prefetch and pipeline schemes.
It is, therefore, another object of the present invention to provide a method for performing a data read operation in a DDR SDRAM that is capable of efficiently issuing two data within one clock by using two-bit prefetch and pipeline schemes.
In accordance with one aspect of the present invention, there is provided a double data rate (DDR) synchronous dynamic random access memory (SDRAM), comprising: a memory cell core circuit for simultaneously accessing two memory cells and prefetching data stored in the two memory cells, wherein the two memory cells include first and second memory cells, the first and second memory cells storing first and second bit data, respectively; a signal generating means for generating signals to synchronize the first and second bit data with rising and falling edges of a clock and control an issue of the first and second bit data; and a pipeline latch means for latching the first and second bit data prefetched by said memory cell core circuit and issuing the first and second bit data in response to the signals generated by said signal generating means.
In accordance with another aspect of the present invention, there is provided a method for performing a read data operation in a double data rate (DDR) synchronous dynamic random access memory (SDRAM), comprising the steps of: a) simultaneously accessing two memory cells and prefetching data stored in the two memory cells, wherein the two memory cells store first and second bit data, respectively; b) latching the first and second bit data; c) generating signals to synchronize the first and second bit data with rising and falling edges of a clock and control an issue of the first and second bit data; and d) issuing the first and second bit data in response to the generated signals.
REFERENCES:
patent: 5892730 (1999-04-01), Sato et al.
patent: 6011751 (2000-01-01), Hirabayashi
patent: 6016280 (2000-01-01), Maesako et al.
patent: 6044032 (2000-03-01), Li
Han Jong-Hee
Yun Mi-Kyung
Ho Hoai V.
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Nelms David
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