Patent
1996-11-21
1998-08-18
Ellis, Richard L.
395382, G06F 932
Patent
active
057969981
ABSTRACT:
An apparatus and method for fetching instructions in an information handling system operating at a predetermined number of cycles per second includes an instruction cache for storing instructions to be fetched. Branch target calculators are operably coupled to instruction queues and to a fetch address selector for determining, in parallel, if instructions in the instruction queues are branch instructions and for providing, in parallel, a target address for each of the instruction queues to the fetch address selector such that the fetch address selector can provide the instruction cache with one of the plurality of target addresses as the next fetch address. Decoding of instructions, calculating the target addresses of branch instructions, and resolving branch instructions are performed in parallel instead of sequentially and, in this manner, back-to-back taken branches can be executed at a rate of one per cycle.
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Levitan David Stephen
Muhich John S.
Talcott Adam R.
White Steven W.
Ellis Richard L.
England Anthony V. S.
International Business Machines - Corporation
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