Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1997-06-12
1999-11-09
Moise, Emmanuel L.
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
712209, 712226, G06F 1500, G06F 900, G06F 930
Patent
active
059833378
ABSTRACT:
A superscalar microprocessor implements instruction level patching. A instruction fetch unit includes a register for storing opcodes of instructions to be patched. When an instruction is fetched, the instruction fetch unit compares the opcode of the fetched instruction to the opcode stored in the patch opcode register. If the opcode of the fetched instruction matches an opcode stored in the patch opcode register, the instruction is dispatched to a microcode instruction unit. The microcode instruction unit invokes a patch microcode routine that dispatches a plurality of microcode instruction that causes a substitute microcode instruction stored in external memory to be loaded into patch data registers. The microcode instruction unit then dispatches the substitute instruction stored in the patch data registers and the substitute instruction is executed by a functional unit in place of the original instruction.
REFERENCES:
patent: 4028678 (1977-06-01), Moran
patent: 4028679 (1977-06-01), Divine
patent: 4028683 (1977-06-01), Divine et al.
patent: 4044338 (1977-08-01), Wolf
patent: 4400798 (1983-08-01), Francis et al.
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4482953 (1984-11-01), Burke
patent: 4542453 (1985-09-01), Patrick et al.
patent: 4610000 (1986-09-01), Lee
patent: 4802119 (1989-01-01), Heene et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 4982360 (1991-01-01), Johnson et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5053949 (1991-10-01), Allison et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5212693 (1993-05-01), Chao
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5295247 (1994-03-01), Chang et al.
patent: 5321830 (1994-06-01), Nakamura et al.
patent: 5333292 (1994-07-01), Takemoto et al.
patent: 5367571 (1994-11-01), Bowen et al.
patent: 5379301 (1995-01-01), Sato et al.
patent: 5425036 (1995-06-01), Liu et al.
patent: 5440632 (1995-08-01), Bacon et al.
patent: 5454100 (1995-09-01), Sagane
patent: 5481713 (1996-01-01), Wetmore et al.
patent: 5535329 (1996-07-01), Hasting
patent: 5636374 (1997-06-01), Rodgers
patent: 5694587 (1997-12-01), Webb et al.
patent: 5713035 (1998-01-01), Farrell et al.
patent: 5742794 (1998-04-01), Potter
patent: 5790843 (1998-08-01), Borkenhagen
patent: 5790860 (1998-08-01), Wetmore
patent: 5794063 (1998-08-01), Favor
patent: 5796972 (1998-08-01), Johnson et al.
patent: 5796974 (1998-08-01), Goddard et al.
patent: 5799144 (1998-08-01), Mio
patent: 5829012 (1998-10-01), Marlan et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
IBM Technical Disclosure Bulletin entitled, "On-Site ROS Patch Mechansim," vol. 30, No. 5, Oct. 1987, New York, USA, pp. 158-160, XP002013790.
Scherpenberg, F.A., et al., Electronics De 1984 A 1985: Electronics Week, "Asynchronous Circuits Accelerate Access to 256-K Read-Only Memory," pp. 141-145, XP002013791.
Mahalingaiah Rupaka
Tran Thang
Advanced Micro Devices , Inc.
Chase Shelly A
Kivlin B. Noel
Merkel Lawrence J.
Moise Emmanuel L.
LandOfFree
Apparatus and method for patching an instruction by providing a does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for patching an instruction by providing a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for patching an instruction by providing a will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1470434