Apparatus and method for partial execution blocking of instructi

Boots – shoes – and leggings

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395479, 395180, 364DIG1, G06F 1200

Patent

active

054559243

ABSTRACT:
A partially blocking data cache having improved microprocessor performance while maintaining data consistency between external memory and cache memory. The data cache of the present invention is used in a computer system and is partially blocking in that this cache will block the execution of any store instructions subsequent to an outstanding load instruction that missed the cache. The present invention offers increased microprocessor efficiency by allowing execution of subsequent load instructions while less than a predetermined number of preceding load instructions are still outstanding. The present invention utilizes a counter within the data cache unit to track the number of outstanding load misses. The present invention provides increased performance without undue or overly complex modifications to existing caching systems. The present invention operates advantageously within a computer system having a relatively large number of registers associated with the microprocessor such that store instructions represent a relatively small number of the instructions executed by the microprocessor.

REFERENCES:
patent: 4884197 (1989-11-01), Sachs et al.
patent: 5025366 (1991-06-01), Baror
patent: 5222224 (1993-06-01), Flynn et al.

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