Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Patent
1997-12-23
1999-11-02
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
712208, 712209, 712212, 712200, G06F 930
Patent
active
059788992
ABSTRACT:
Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.
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Beerel Peter A.
Ginosar Ran
Kol Rakefet
Myers Christopher John
Rotem Shai
An Meng-Ai T.
Intel Corporation
Whitmore Stacy
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