Boots – shoes – and leggings
Patent
1992-02-28
1994-12-20
Dixon, Joseph L.
Boots, shoes, and leggings
364DIG1, 3642599, 3642625, G06F 1202
Patent
active
053752163
ABSTRACT:
A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.
REFERENCES:
patent: 3858182 (1974-12-01), Delagi et al.
patent: 4719568 (1988-01-01), Carrubba et al.
patent: 5148528 (1992-09-01), Fite et al.
patent: 5255378 (1993-10-01), Crawford et al.
George Radin, "The 801 Minicomputer", paper published in the ACM SIGARCH Computer Architecture News, vol. 10, No. 2, Mar. 1982, pp. 212-221.
IBM RT PC Hardware Technical Reference, vol. 1, Third Edition, technical manual for a version of the 801 Minicomputer, published Jun. 1988 pp. 11-12,-14,-16,-24, and -25.
Keith Diefendorff, "The 88110: A Superscalar Microprocessor with Graphics Support", (slides and transcript of speech presented at Microprocessor Forum on Nov. 6, 1991).
Keith Diefendorff, "The 88110: A Superscalar Microprocessor with Graphics Support", (preliminary sides provided Sep. 1991 for presentation of Microprocessor Forum on Nov. 6, 1991).
Keith Diefendorff and Michael Allen, "Organization of the Motorola 88110: A Superscalar RISC Microprocessor", Proceedings of Intl. Processing Society of Japan, Nov. 1991, pp. 77-87.
Keith Diefendroff and Michael Allen, "Organization of the Motorola 88110: A Superscalar RISC Microprocessor", sent to publisher for publication in 192 COMPCON Proceedings, to be published Feb. 24, 1992.
Keith Diefendorff and Michael Allen, "The Motorola 88110 Superscalar RISC Microprocessor", preliminary slides for presentation at COMPCON to be held on Feb. 24, 1992.
Keith Diefendorff and Michael Allen, "Organization of the Motorola 88110 Superscalar RISC Microprocessor", IEEE Micro, submitted to IEEE on Dec. 13, 1991 (not published yet).
Keith Diefendorff and Michael Allen, "Organization of the Motorola 88110 Superscalar RISC Microprocessor", IEEE Micro, submitted to IEEE on Jan. 21, 1992 in revised form (not published yet).
MC88100 RISC Microprocessor User's Manual, Second Edition, published by Motorola, Inc. in 1990, pp. 1-, 2-1, 2-2, 3-85, 3-86, and 3-87.
MC88200 Cache/Memory Management Unit User's Manual, Second Edition, published by Motorola, Inc, in 1990, pp. 2-4, 2-5, and 2-8.
Arends John H.
Diefendorff Keith E.
Moyer William C.
White Christopher E.
Apperley Elizabeth A.
Dixon Joseph L.
Motorola Inc.
Nguyen Hiep T.
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