Apparatus and method for optimizing delay element in...

Details Apparatus and method for optimizing delay element in... Apparatus and method for optimizing delay element in...

2011-04-26

2011-04-26

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S113000, C716S114000, C716S134000

Reexamination Certificate

active

07934186

ABSTRACT:
A computer readable storage medium includes executable instructions to construct a delay element to replicate the timing of critical gates and paths within a segment of an asynchronous circuit. The rise and fall delay mismatch of the delay element is minimized without obeying timing constraints. The position of each output of the delay element is determined to include a globally shared node within the segment and a non-shared local node in the segment.

REFERENCES:
patent: 6553550 (2003-04-01), Menegay et al.
patent: 2002/0175705 (2002-11-01), Lowy et al.
patent: 2003/0177455 (2003-09-01), Kaufman et al.
patent: 2004/0210857 (2004-10-01), Srinivasan
patent: 2005/0046458 (2005-03-01), Schroeder et al.
patent: 2005/0216247 (2005-09-01), Ikeda et al.
patent: 2006/0288320 (2006-12-01), Murgai et al.
PCT US08/78319 ISR, Sep. 30, 2008, Nanochromous Logic.

Affiliated with

Also associated with

Rating

Apparatus and method for optimizing delay element in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for optimizing delay element in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for optimizing delay element in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2664011