Apparatus and method for optimal error correcting code to parity

Details Apparatus and method for optimal error correcting code to parity Apparatus and method for optimal error correcting code to parity

1994-07-05

1995-12-19

Canney, Vincent P.

Excavating

371 376, 371 491, G06F 1110

Patent

active

054775515

ABSTRACT:
This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems by reducing the memory latency incurred in the ECC to parity conversion process.

REFERENCES:
patent: 4862462 (1989-08-01), Zulian
patent: 5182752 (1993-01-01), DeRoo et al.
patent: 5289477 (1994-02-01), Lenta et al.
patent: 5375127 (1994-12-01), Leak et al.

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