Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-01-16
2003-07-22
Lam, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S236000, C365S189090, C365S203000
Reexamination Certificate
active
06597622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a multi-bank semiconductor memory device that is capable of varying a driving capability of a voltage driving circuit according to the number of accessed banks.
2. Description of the Background Art
As shown in
FIG. 1
, a conventional multi-bank semiconductor memory device includes a memory
10
having
16
banks, two bank address decoders
12
and
14
, a controller
16
and a voltage generator
18
.
The bank address decoder
12
decodes active bank addresses ABA
0
~ABA
3
and generates bank precharge signals BAC
0
-BAC
15
. The bank address decoder
14
decodes precharging bank addresses PBA
0
~PBA
3
and generates bank precharge signals BPR
0
-BPR
15
.
RACC and RPRE respectfully correspond to a low access signal and a low precharge signal, which are RAS signals of DRAM. That is, the RACC performs the same function as a negative edge of the RAS signal, and the RPRE performs the same function as a positive edge of the RAS signal.
The controller
16
receives bank access signals BAC
0
~BAC
15
and BPR
0
-BPR
15
outputted from the two bank address decoders
12
and
14
, and a driving enable signal DREN for driving the voltage generator
18
according to the bank precharge signals BPR
0
~BPR
15
.
As shown in
FIG. 2
, the controller
16
includes a plurality of latches (LAT
1
~LATn) and one AND gate AD
1
. An initial state of the latches (LAT
1
~LATn) is determined by a power up (PWRUP) signal.
The voltage generator
18
generates every power supply voltage VDD required for a memory device and includes one standby driving circuit
18
-
1
and a plurality of active driving circuits
18
-
2
~
18
-
n
The standby driving circuit
18
-
1
is continuously operated, while the active driving circuits
18
-
2
~
18
-
n
are operated according to the driving enable signal DREN outputted from the controller
16
.
The operation of the multi-bank semiconductor memory device of the conventional art constructed as described above will now be explained.
Two bank address decoders
12
and
14
are synchronized by the low access signal RACC or the low precharge signal RPRE and decode an inputted bank address. Then, the two bank address decoders
12
and
14
generate bank access signals BAC
0
~BAC
15
and bank precharge signals BPR
0
~BPR
15
, respectively.
That is, in reading/writing operations of the memory
10
, the bank address decoder
12
decodes the bank addresses ABA
0
~ABA
3
synchronized with the low level low access signal RACC and outputs the bank access signals BAC
0
~BAC
15
to the controller
16
.
Meanwhile, in precharging of the memory
10
, the bank address decoder
14
decodes the bank addresses PBA
0
~PBA
3
synchronized with the high level low precharge signal RPRE and outputs bank precharge signals BPR
0
~BPR
15
to the controller
16
.
The controller
16
receives the bank addresses ABA
0
~ABA
3
or the bank precharge signals BPR
0
~BPR
15
of each bank, and generates the driving enable signal DREN for driving the voltage driving circuits
18
-
2
~
18
-
n
of the voltage generator
18
.
Namely, the controller
16
includes latches LAT
1
~LATn indicating whether 16 banks are accessed or precharged and an AND gate AD
1
for generating the driving enable signal DREN when at least one bank is accessed.
When an access signal of a specific bank is inputted, the controller
16
sets the latch, and conversely, when a precharge signal is inputted, the controller resets the latch. At this time, the power-up (PWRUP) signal serves to reset the initial state of the latches LAT
1
~LATn.
Accordingly, during an interleaving operation, since a plurality of banks are accessed, the latches LAT
1
~LATn are set according to the number of accessed as banks. That is, the number of set latches indicates the number of banks currently performing an interleaving operation.
The voltage generator
18
operates every active voltage driving circuit
18
-
2
~
18
-
n
according to the driving enable signal DREN outputted from the controller
16
and generates a power supply voltage VDD required for the memory device. At this time, the standby driving circuit
18
-
1
is operated all the time.
The conventional multi-bank semiconductor memory device, however, has the following problems.
That is, first, the bank addresses ABA and PBA inputted in synchronization with the low access signal RACC or the low precharge signal RPRE are decoded by the respective bank address decoder
12
or
14
and inputted to the controller
16
. Accordingly, a delay time occurs before the driving enable signal DREN of the voltage generator
18
is generated. Such time delay causes delay in the response of the voltage generator
18
, causing an unstable operation of the memory.
Second, as the number of banks is increased in the memory
10
, the bank addresses decoded by the bank address decoders
12
and
14
are increased to cause a problem that a routing area is enlarged.
Third, as the number of banks of the memory
10
is increased, the number of logic gates in the controller
16
and the input number of the logic gates are increased. Then, a lay-out area of the controller
16
is accordingly increased, serving as a factor delaying generation of the driving enable signal DREN.
Fourth, since the voltage driving circuits included in the voltage generating circuit are divided into two types of circuits including a standby circuit and an active circuit, if the number of banks for performing an interleaving operation is increased, it is difficult to suitably cope with it. The reason for this is that the number of the active driving circuits should be increased according to the number of the banks for performing the interleaving operation.
Fifth, if even one bank of the voltage generating circuit is accessed, every active driving circuit is operated. Thus, power is unnecessarily consumed.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a multi-bank semiconductor memory device that is capable of varying a driving capability of a voltage generator according to the number of active banks.
Another object of the present invention is to provide a multi-bank semiconductor memory device that is capable of stably operating a memory by increasing a response speed of the voltage generator.
A further object of the present invention is to provide a multi-bank semiconductor memory device that is capable of almost constantly maintaining a lay-out area regardless of the number of banks performing an interleaving.
Still another object of the present invention is to provide a multi-bank semiconductor memory device that is capable of optimizing a power consumption by varying the number of active driving circuits according to the number of active banks.
To achieve these and other advantages one embodiment of the invention includes a semiconductor device including a memory having memory banks and generating a first signal and a second signal; a voltage generator having a plurality of driving circuits and generating a power required for operation of the semiconductor memory device; and, a counter for receiving a first signal and a second signal and generating a count value and a corresponding driving signal for driving a first number of active driving circuits of the plurality of driving circuits such that the first number of active driving circuits is variable.
The counter counts the first signal and the second signal to generate the drive signal. Also, when a number of memory banks N of the memory banks in the memory are active, the driving signal has a value of logN bit. Further, the first signal is a low access signal, and the second signal is a low pre-charge signal.
The first number of active driving circuits may be equal to the count value determined by the counter. Also, the first number of active driving circuits may be sequentially driven according the count value determined by the counter. On the other hand, the first number active driving circuits may be variably d
Lee Joo-Sang
Park Jong-Hoon
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Lam David
LandOfFree
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