Patent
1996-07-29
1998-09-22
Lall, Parshotam S.
395569, G06F 938
Patent
active
058128131
ABSTRACT:
An apparatus and method for improving the execution speed of particular micro instruction sequences is provided, and which allows for exception handling of the micro instruction sequences, as needed. During execution of a micro instruction sequence, particular registers are allowed to be overwritten prior to completion of the entire micro instruction sequence. A tracking mechanism is provided which tracks which registers are overwritten, and restoration logic is provided which stores the "old" contents of the particular registers. If the micro instruction sequence cannot complete, due to a fault, for example, the tracking mechanism indicates which registers have been overwritten, and the restoration logic provides the "old" values to be restored.
REFERENCES:
patent: 4901233 (1990-02-01), Liptay
patent: 4970641 (1990-11-01), Hester et al.
patent: 5247624 (1993-09-01), Koumoto et al.
patent: 5355437 (1994-10-01), Shebanow et al.
Henry Glenn
Parks Terry
Huffman James W.
Integrated Device Technology Inc.
Lall Parshotam S.
Vu Viet
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