Apparatus and method for non-destructive, low stress removal...

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Reexamination Certificate

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Details

C219S392000, C219S393000, C228S119000, C228S264000

Reexamination Certificate

active

06333491

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention pertains to an apparatus and method for removing soldered electronic components from a substrate. More particularly, it relates to non-destructive, low stress removal of chips temporarily soldered to a substrate during Known-Good-Die (KGD) processing of flip chip devices.
1. Background Art
As technology has evolved, semiconductor devices have become smaller and more dense, which has resulted in corresponding increases in overall chip failure rates, which in turn results in uncompetitive situations for chip manufacturers. In order to readily identify and eliminate the use of defective chips before the defective chips are finally mounted in a product, burn-in processes have evolved. During the burn-in process, normally a chip carrier is provided for testing the chips. The chip carrier has electrical contacts which correspond to the electrical contacts on the semiconductor chip. It is desirable for the carrier contacts to be mechanically weak but strong enough for holding the semiconductor chip in place and to maintain good electrical connections during testing. The chip is normally positioned on the chip carrier so that the electrical contacts, e.g., solder balls, on the chip are aligned with the corresponding contacts on the carrier and then the solder balls make electrical connections between the chip and the carrier.
In one process for the manufacture of KGD flip chip devices, silicon chips are temporarily attached by solder balls (typically a SnPb alloy, such as 3% tin (Sn) and 97% lead (Pb), referred to as 3/97 solder) to a composite or ceramic substrate, or chip carrier, and subjected to electronic component testing and burn-in. Following this testing, the chips are mounted in a first fixture and subjected at ambient temperature to shear forces across the solder balls to remove the chip from the substrate. These forces typically fracture the solder balls, leaving some solder attached to the substrate and some to the chip. Thereafter, the chips are removed from the first fixture, and those which tested as good mounted in a second fixture for heat processing to liquify the solder on the chip and reform the solder balls. The resulting chips are then packaged and eventually mounted in an array of chips on another substrate.
A variety of processes and techniques have been devised and described in the art to form a temporary connection between semiconductor chips and carriers, so as to be able to readily separate the chip and the carrier after burn-in tests have been conducted. Several of these are described in U.S. Pat. No. 5,556,024 by David C. Olson and Robert Phillips, III, and of common assignee, for “Apparatus and Method for Removing Known Good Die Using Hot Shear Process”, the teachings of which are incorporated herein by reference. In the improved process which is the subject of the Olson and Phillips patent, the carrier and the device are placed in a fixture, heated to the solder liquidus temperature, and the device pulled away from the substrate. In one embodiment, after being heated to the solder liquidus temperature, shear forces are applied sufficient to overcome solder surface tension and separate the die and carrier. This type of separation occurs within the solder joint such that only part of the solder remains on the chip, thus requiring an additional step of site dressing whereby the required solder volume is restored to the chip pad sites so that the KGD chip can be subsequently permanently assembled into a microelectronic package.
It is an object of the invention to provide an improved method and apparatus for separating chips from chip carriers.
It is a further object of the invention to provide an improved method and apparatus for processing KGD chips, to remove them from the chip carrier while the solder connections are solid, such that substantially all of the solder remains attached to the chip.
It is a further object of the invention to provide an apparatus for removing chips from substrates where the force required is substantially the same for all chips or rows of chips.
It is a further object of the invention to provide a cascade effect apparatus and method for sequentially removing chips or rows of chips from one or more chip carriers, or substrates.
It is a further object of the invention to provide an apparatus comprising a single fixture for removing chips from a chip carrier and reforming the solder on the chips.
SUMMARY OF THE INVENTION
In accordance with the invention, an apparatus and method is provided for removing circuit chips from an assembly including a one or more circuit chips attached to at least one chip carrier, or substrate. The chips are subjected to static shear with respect to the substrate, and heated to a temperature facilitating shear within a temperature range at which solder connections are solid, such that the chip is sheared off with respect to the substrate at the plane of attachment of the solder to the substrate. In accordance with a further aspect of the invention, the chips are further heated following disassembly to a temperature at which the solder is liquid to facilitate reforming the solder for subsequent attachment of the chip into an electronic device.
In accordance with a further aspect of the invention involving the removal of a plurality of circuit chips from one or more substrates, the substrate is held within a top plate with the circuit chips positioned within successive chip cavities within a bottom plate. Each chip cavity includes a load surface separated by a cascade effect pitch with respect to adjacent chip cavities. A cascade effect shear force is sequentially applied to the circuit chips to remove them from the substrate.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4274576 (1981-06-01), Shariff
patent: 5154793 (1992-10-01), Wojnarowski et al.
patent: 5174016 (1992-12-01), Todd
patent: 5237269 (1993-08-01), Aimi et al.
patent: 5556024 (1996-09-01), Olson et al.
patent: 5636781 (1997-06-01), Olson et al.
patent: 5707000 (1998-01-01), Olson et al.
patent: 5722579 (1998-03-01), Yu et al.
patent: 5738267 (1998-04-01), Olson et al.
patent: 5779133 (1998-07-01), Jackson et al.
patent: 19808728 (1998-09-01), None
patent: 305696 (1989-03-01), None
patent: 10-247779 (1998-09-01), None

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