Patent
1997-02-28
1999-06-01
An, Meng-Ai T.
395385, 395389, 39580041, G06F 930
Patent
active
059095679
ABSTRACT:
A processor reduces or avoids a degradation of computing performance in a computer system using a RISC-based CISC processor by selectively bypassing a CISC-to-RISC translator or decoder and supplying native RISC codes directly to the RISC core. The processor that executes CISC-type instructions on a RISC core includes a native mode Op supply circuit for supplying RISC Ops directly from an instruction memory to a RISC execution engine.
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Ma Siyad C.
Novak Steven
Advanced Micro Devices , Inc.
An Meng-Ai T.
El-Hady Nabil
Koestner Ken J.
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