Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-11-27
1998-02-10
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518501, 36518503, 36518524, G11C 1134
Patent
active
057176329
ABSTRACT:
A storage control circuit determines a programmed threshold voltage V.sub.tP of a storage cell in which the transistor threshold voltages V.sub.tT of the cell may overlap while the logical threshold voltages V.sub.tL remain distinct. In one embodiment, sixteen distinctive levels are stored in a storage cell within a 2.5 V range so that a single memory cell supplies four bits of information storage per cell, quadrupling the memory capacity per cell as compared to conventional single-bit storage cells. In an embodiment, a nonvolatile memory circuit includes a nonvolatile memory array with a plurality of memory cells and a plurality of decoders connected to the nonvolatile memory array. The plurality of decoders decode addresses to the nonvolatile memory array. The nonvolatile memory circuit also includes a voltage controller connected to the nonvolatile memory array, a programming controller connected to the plurality of decoders and connected to the voltage controller, a plurality of sense amplifier and reference cells connected to the plurality of decoders for sensing a memory cell at a selected memory cell address of the plurality of memory cells in the nonvolatile memory array and connected to the programming controller for receiving the sensing mode signal, and a level conversion circuit having input terminals connected to the plurality of sense amplifier and reference cells and having an output terminal connected to the programming controller for communicating a level feedback signal. The voltage controller controls a programming voltage amplitude applied to the nonvolatile memory array. The programming controller selects a memory cell address, a nonvolatile memory array programming voltage amplitude, and a sensing mode signal.
REFERENCES:
patent: 5596527 (1997-01-01), Tomioka et al.
patent: 5619452 (1997-04-01), Miyauchi
M. Bauer, et al. "A Multilevel-Cell 32Mb Flash Memory", 1995 IEE International Solid State Circuits Conference, Feb. 16, 1995, pp. 132-133.
K. Yoshikawa, "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", 1996 Symposium on VLSI Technology Digest of Technical Papers, , IEEE, 1996, pp. 240-241.
Garg Shyam
Richart Robert B.
Advanced Micro Devices , Inc.
Koestner Ken J.
Nelms David C.
Niranjan F.
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