Apparatus and method for modeling a graded channel transistor

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364578, 3642212, 3642323, 3642643, 3642756, G06F 9455, G06F 1750

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056873557

ABSTRACT:
The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable. Steps are also disclosed for manufacturing integrated circuits using the modeling techniques of the present invention.

REFERENCES:
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patent: 5208475 (1993-05-01), Montensen
patent: 5345401 (1994-09-01), Tani
patent: 5467291 (1995-11-01), Fan et al.
patent: 5481485 (1996-01-01), Takeuchi
patent: 5502643 (1996-03-01), Fujinaga
patent: 5553008 (1996-09-01), Huang et al.
patent: 5600578 (1997-02-01), Fang et al.

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