Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-06-15
2003-03-18
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S760000
Reexamination Certificate
active
06534870
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus and a method for manufacturing a semiconductor device having a wiring structure between inter-layer insulating films. The present invention also relates to an apparatus and a method for manufacturing a semiconductor device having a multilayer wiring structure on a substrate where transistors are formed.
Due to downsizing of wiring sizes, the wiring resistance and wiring capacitance tend to steadily increase and have come to greatly affect the operation frequency and power consumption of the devices. Hence, to reduce the wiring capacitance and to realize higher performance of the device, studies and developments have been eagerly made with respect to an SiO
2
film (FSG), an organic SiO
2
film, an organic film, and the like added with F having a low dielectric constant, in place of an SiO
2
film (P—SiO
2
film) formed by a plasma CVD method which has been conventionally used as an inter-layer insulating film.
Any of those materials, however, has advantages and disadvantages compared with the P—SiO
2
film, so that various problems exist in application of those materials to inter-layer insulating films in an LSI.
A problem concerning an FSG film is reduction of moisture absorption caused when F is added at a high concentration (the dielectric constant decreases in proportion to the addition amount of F) and is left in the atmosphere. Where this moisture absorption is considered, it is known that the practical application range of the FSG film is 3.3 or more.
Meanwhile, the organic SiO
2
film has an excellent moisture-absorption resistance even in case of a material having a low dielectric constant of 3.0 or less. However, there is a problem that it is not possible to perform processing of a fine hole pattern which causes cracking due to an O
2
plasma used for peeling a resist. Taking into consideration these problems, it has been difficult to adopt an organic SiO
2
film of a single layer film as an inter-layer insulating film in an LSI.
Therefore, discussion is made as to application of a combination of an organic SiO
2
film and, for example, an inorganic film of SiN, SiO
2
, FSG, or the like to an inter-layer insulating film in a multilayer wiring. However, the dielectric constant is higher compared with the case of using an organic SiO
2
film as a single layer. In addition, in case where organic SiO
2
films are multilayered into four or five layers, there is a problem that cracking is caused in heating steps or peeling occurs in CMP steps. As a result, it has been difficult to prepare a multilayer wiring which provides high reliability by the combination of an organic film and an inorganic film.
The above problems will be explained with reference to the drawings.
FIG. 1
is a cross-sectional view showing a semiconductor device which realizes a multilayer structure by combining a silicon oxide film and an FSG film. The reference
81
denotes a P—SiO
2
film and the references
84
,
88
,
92
,
96
, and
100
are respectively first to fifth Al wirings. FSG films are used for
85
,
89
,
93
, and
97
as inter-layer films. Also, the references
82
,
86
,
90
,
94
, and
98
are inter-wiring films, i.e., films which insulate wirings in one same wiring layer from each other and organic silicon oxide films having a predetermined carbon concentration are used for the inter-wiring films. Also, Nb films are used for the references
83
,
87
,
91
,
95
, and
99
as liner materials. In this multilayer structure, cracking
101
occurs due to a stress in the organic silicon oxide film as a inter-wiring film of the Al wiring
84
which is in the lowermost layer.
FIG. 2
shows a single wiring structure, and the reference
111
is an organic silicon oxide film having a BPSG film on which devices not shown are formed, and the references
112
and
113
are organic silicon oxide films having a predetermined carbon concentration. In case of manufacturing this wiring structure, an anti-reflection film (ARL) and a resist are applied and developed when patterning an organic silicon oxide film
113
. RIE is used to process a groove. However, if RIE using an O
2
gas is used to remove the anti-reflection and resist, cracking
114
occurs at the bottom portion of the groove.
FIG. 3
is an enlarged view of a main part of a wiring structure, like FIG.
2
. The reference
121
denotes a P—SiO
2
film, and the reference
122
denotes an organic silicon oxide film having a predetermined carbon concentration. An Al wiring
124
is formed in a groove portion formed in the organic silicon oxide film
122
, with an Nb film
123
as a liner material interposed. On the Al wiring
124
and the organic silicon oxide film
122
, an organic silicon oxide film
125
having a predetermined carbon concentration is formed as an inter-layer film. Also, to make contact with Al wiring
124
, a hole from which the Al wiring
124
is exposed is formed in the organic silicon oxide film
125
.
If etching is performed during formation of this hole, etching sufficiently reaches the bottom surface in case of forming a hole
126
having relatively loose dimensions. Otherwise, in case of forming a hole
127
having a fine small hole
127
, a polymerized product contained in the organic silicon oxide film
126
is created. If this polymerized product is created, there appears a phenomenon of etch-stop in which the resist merely shifts back and stops halfway, resulting in a problem that the etching cannot sufficiently reaches the Al wiring
124
.
Thus, in case of a conventional wiring structure, cracking occurs in an inter-layer insulating film in a heating step and during peeling of a resist. A problem hence appears in that the etch-stop occurs during formation of a wiring groove.
Meanwhile, in a multilayer wiring of a large scale integrated circuit (LSI), the following problem has been cited. An upper-layer wiring is constructed under looser rules than a lower-layer wiring, and the width and thickness of the upper-layer wiring are two to four times larger than those of the lower-layer wiring. For example, the uppermost-layer wiring of a logic device having a gate length of 0.25 &mgr;m has a wiring width and a wiring thickness which respectively reach 2.2 &mgr;m and 1.6 &mgr;m. This wiring has a seven times larger compared with the first-layer wiring, as well as a three times larger thickness. This is to restrict the RC delays of the signal wirings as much as possible. The resistance component is decreased by increasing the cross-sectional area of the wiring, and the inter-wiring capacitance component and the inter-layer distance capacitance component are decreased by increasing the inter-wiring distance and the inter-layer distance. In this case, since the size in the thickness direction is increased, the film thickness must be increased with respect to an insulating film (hereinafter called an inter-layer insulating film) corresponding to the portion of the wiring layers on the structure.
However, even an insulating film made of one single layer cannot be deposited as thick as possible. Problems appearing when an insulating film is deposited to be thick will be explained with reference to FIG.
4
. The semiconductor device shown in
FIG. 4
is a semiconductor device which has a wiring structure of n layers. inter-wiring insulating films
2
,
6
,
14
, and
17
and inter-layer insulating films
4
,
8
,
10
, and
14
are alternately formed on a semiconductor substrate
1
. Further, a first-layer wiring
3
, a second-layer wiring
7
, an (n−1)-th-layer wiring layer, and an n-th-layer are consecutively formed between the insulating films, thereby forming a wiring structure of n layers. In this semiconductor device, it has been found that both the wiring width and thickness of the (n−1)-th-layer wiring
13
and the n-th-layer wiring
18
are larger than the first-layer-wiring
3
and the second-layer-wiring
7
.
However, if the film thickness of the (n−1)-th-layer wiring
13
and that of the n-th-layer wiring
18
reach a certa
Kawai Motonobu
Matsunaga Noriaki
Miyajima Hideshi
Nakata Rempei
Shibata Hideki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Flynn Nathan J.
Kabushiki Kaisha Toshiba
Quinto Kevin
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