Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
2002-06-20
2004-07-13
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S694000, C438S702000, C438S717000, C438S725000, C438S692000, C438S724000, C438S723000
Reexamination Certificate
active
06762128
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing. More particularly, the present invention relates to an apparatus and a method for tailoring the total ionizing (radiation) dose (TID) tolerance of semiconductor devices and circuits.
BACKGROUND OF THE INVENTION
State-of-the-art integrated circuits (“ICs”) consist of hundreds of thousands or even millions of transistors and other devices. The spacing between adjacent transistors in such circuits is quite small and electrical leakage between devices does occur. Isolation structures are therefore required to block such leakage currents.
Local oxidation of silicon processes (“LOCOS”) are often used in the fabrication of ICs to provide electrical isolation. LOCOS may not, however, be the preferred isolation method for high-device-density, state-of-the-art ICs. In particular, due to its characteristic “bird's beak” spur, LOCOS uses a relatively large amount of chip “real estate.” Rather, a technique called shallow trench isolation (“STI”), which uses less chip real estate, is preferred.
The use of STI is illustrated in
FIG. 1
, wherein two “shallow” trenches
116
and
118
are employed to electrically isolate a field effect transistor (FET)
100
from adjacent devices (not shown). To provide such isolation, the trenches are filled with an electrically-insulating material, such as silicon dioxide. As depicted in
FIG. 1
, the trenches flank FET
100
, wherein trench
116
is to the “left” of drain
102
, and trench
118
is to the “right” of source
104
.
In the past, complementary metal oxide semiconductor (“CMOS”) processes that incorporated LOCOS-based field isolation and thick “gate oxides” for producing transistors and other devices required special steps to “harden” such devices to ionizing radiation, as is important in aerospace and defense applications. Such ionizing radiation, either from natural or man-made sources, can damage or destroy semiconductor devices. Radiation changes the electrical properties of solid state devices, leading to the possible failure of any system incorporating them. “Radiation hardness” refers to the ability of a semiconductor device to withstand radiation without alteration of its electrical properties. A semiconductor device is termed “radiation hard” (“rad-hard”), “radiation tolerant” or “radiation resistant” if it can continue to function within specifications after exposure to a specified amount of radiation.
Ionizing radiation is one agent that damages or destroys CMOS devices. Ionizing radiation is caused by photon (gamma or x-ray) interactions, fast neutron interactions and charged (alpha and beta) particles. As ionizing radiation is absorbed by a transistor, there is a buildup of positive charge, referred to as “positive charge trapping,” in the field oxide near the silicon-silicon dioxide interface. This charge can interfere with the performance of P-channel devices such as by increasing the threshold voltage, reducing transistor drive current, and reducing speed. In N-channel devices, positive oxide charge causes an inversion of the substrate surrounding the active regions, providing an unwanted current path.
Further discussion of the effects of ionizing radiation on semiconductor devices is provided in applicant's co-pending cases; “Increasing the Susceptibility of Integrated Circuits to Ionizing Radiation” (Docket No. FE-00439); “Semiconductor Circuit Having Increased Susceptibility to Ionizing Radiation” (Docket No. FE00442); and “Semiconductor Device and Circuit Having Low Tolerance To Ionizing Radiation” (Docket No. FE00443), all of which are incorporated by reference herein.
As CMOS technology has scaled to smaller dimensions (i.e., 0.25 micron ground rules and less), the gate oxide has thinned to the point where, by virtue of such thinness, it is inherently relatively impervious to the effects of ionizing radiation. Moreover, as LOCOS is supplanted by STI, the radiation-susceptible semi-thick “bird's beak” region under the polysilicon gate of a transistor is no longer present.
As a result, state-of-the-art ICs utilizing STI are much more tolerant to ionizing radiation than ICs utilizing LOCOS. In fact, such circuits may be radiation hardened to the point where Department of Defense export restrictions may be implicated. To the extent that a commercial CMOS fabricator is restricted from freely exporting its chips, it suffers financially. The art would therefore benefit from an IC that possesses that benefits of contemporary processing technologies yet is advantageously susceptible to ionizing radiation.
SUMMARY OF THE INVENTION
A method and an apparatus for manufacturing, via a single fabrication line, circuits that are relatively tolerant to ionizing radiation and also circuits that are relatively intolerant to ionizing radiation, are disclosed.
In accordance with the present invention, when production calls for radiation-intolerant circuits, a method is used to deposit an insulator that generates a relatively large amount of “positive charge traps” when exposed to ionizing radiation. One method that is suitable for depositing such an insulator is high-density plasma chemical vapor deposition (HDPCVD).
Alternatively, when a radiation-tolerant circuit is desired, a method is used to deposit an insulator that generates relatively fewer “positive charge traps” when exposed to ionizing radiation. Low-pressure chemical vapor deposition (LPCVD) is advantageously used for this purpose. In a further embodiment, plasma-enhanced chemical vapor deposition (PECVD) is used to deposit the insulator for a radiation-tolerant circuit.
The mechanisms by which such oxides impart radiation tolerant and intolerance to such semiconductor devices is described later in this Specification.
One illustrative embodiment of the present invention is an apparatus comprising: trench-forming systems that are collectively operable to form a trench in a wafer; a first processing system operable to deposit an electrically-insulating material in the trench suitable for forming a radiation-tolerant circuit; and a second processing system operable to deposit an electrically-insulating material in the trench suitable for forming a radiation-intolerant circuit. In a first variation of the first illustrative embodiment, the apparatus further comprises a delivery system operative to deliver the wafer to the trench-forming systems, the first processing system and the second processing system.
A second illustrative embodiment of the present invention is an apparatus for fabricating radiation-intolerant and radiation tolerant circuits, comprising: a high-density plasma chemical vapor deposition (HDPCVD) system; and a low-pressure chemical vapor deposition (LPCVD) system. In a first variation of the second illustrative embodiment, the apparatus further comprises a delivery system that is operable to selectively transport the wafer to the HDPCVD system when fabricating the radiation intolerant circuits; and operable to selectively transport the wafer to the LPCVD system when fabricating the radiation tolerant circuits.
A further illustrative embodiment of the present invention is a method for manufacturing radiation tolerant and radiation intolerant circuits in a single fabrication line, the method comprising: forming a trench in a wafer; directing the wafer to one of two systems for filling the trench, as follows: to manufacture a radiation tolerant circuit, to a first system that is operative to deposit an electrically insulating material that, on exposure ionizing radiation, generates an insufficient amount of positive charge trapping centers in said electrically insulating material to render a circuit incorporating same radiation intolerant. To manufacture a radiation intolerant circuit, the wafer is directed to a second system that is operative to deposit an electrically-insulating material that, on exposure to ionizing radiation, generates a sufficient amount of positive charge trapping centers in the electrically-insulating material to render a circuit incorporating same r
Bernkopf Paul A.
Brady Frederick T.
Haddad Nadim
BAE Systems
DeMont & Breyer LLC
Goudreau George A.
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