Apparatus and method for maintaining status flags and condition

Details Apparatus and method for maintaining status flags and condition Apparatus and method for maintaining status flags and condition

1996-08-30

1998-10-20

Lim, Krisna

395393, 39580023, G06F 9302

Patent

active

058260706

ABSTRACT:
An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative instructions. A floating point queue (FPQ) receives speculative instructions and issues out-of-order instructions to FPQ execution units, each instruction containing a group identifier tag (GID) and a target identifier tag (TID). The GID tag indicates a set of instructions bounded by interruptible or branch instructions. The TID indicates a targeted architected facility and the program order of the instruction. The FPSCR contains status and control bits for each instruction and is updated when an instruction is executed and committed. A FPSCR renaming mechanism assigns an FPSCR rename to selected FPSCR bits during instruction dispatch from an instruction fetch unit (IFU) to the FPQ when an arithmetic instruction is dispatched that has a GID which has not been committed by instruction dispatch unit (IDU) and does not already have an FPSCR rename assigned, as determined by the FPQ. The FPSCR rename mechanism utilizes the TID upon the presence of selected bits in the FPSCR. The bits in the FPSCR rename are updated as a new arithmetic instruction enters a write-back stage in the FPU. The resulting FPSCR updates of all instructions in a given GID are merged into one FPSCR rename register. A FPSCR rename register exists for each GID rather than a FPSCR rename register for each FPR rename register as in the prior art.

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