Apparatus and method for maintaining processing consistency in a

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364DIG1, 364DIG2, 3642624, G06F 946

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active

054209919

ABSTRACT:
An apparatus for maintaining processor ordering in a multi-processor computer system wherein loads are performed speculatively. Speculative loads of each processor are temporarily stored in their respective processors' load buffer. When one of the processors performs a store, a snoop operation is performed on the other processors' load buffers. If the snoop results in a hit, a determination is made as to whether that load buffer contains any prior conflicting speculative loads which have been completed. If the load buffer does contain a prior conflicting load, a processor ordering violation signal is generated. In response to this signal, the violating load and all subsequent operations are canceled and re-executed at a later time.

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Val Popescu, et al., "The Metaflow Architecture", Jun. 1991, IEEE Micro, pp. 10-13 and 63-73.

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