Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2002-02-28
2004-01-27
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S204000, C712S206000, C712S210000, C712S213000, C712S215000
Reexamination Certificate
active
06684320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of processors. In particular, the invention is in the field of VLIW (Very Long Instruction Word) processors.
2. Background Art
VLIW (Very Long Instruction Word) processors use an approach to parallelism according to which several instructions are included in a long instruction word which is fetched from memory every clock cycle. The long instruction word fetched from the memory is part of a packet referred to in this application as a VLIW packet or a “packet of instructions.”
Instructions in a VLIW packet can be of different “instruction types.” For example, a certain VLIW packet can have integer ALU type instructions such as “Shift and Add” and “Compare” instructions; non-integer ALU type instructions such as “Shift L Variable,” “Shift R Variable,” “Move to BR,” and “Move from BR” instructions. Other exemplary instruction types in a typical VLIW packet are memory type instructions such as “Integer Load,” “Integer Store,” and “Line Prefetch” instructions; floating point type instructions such as “Floating Point Compare” and “Floating Point Clear Flags” instructions; and branch type instructions such as “Indirect Branch” and “Indirect Call” instructions.
Each of the several instructions in a VLIW packet is placed in a particular “instruction slot.” Each instruction type is usually assigned to one or two specific logic units in a VLIW data path for execution. Each such logic unit is referred to as an “execution unit” in the present application.
The individual instructions in a VLIW packet are arranged in different “issue groups” and there can be a number of issue groups in the VLIW packet. By way of background, a VLIW packet typically contains a number of instructions which can be executed in the same clock cycle. Instructions in a VLIW packet which can be executed in the same clock cycle form a single “issue group.” By definition, instructions belonging to a same issue group do not depend on the result of execution of other instructions in that same issue group. However, instructions in one issue group may depend on the result of execution of instructions in another issue group. The “length” of an issue group specifies how many instructions are in that issue group. For example, a particular issue group may have a length of two instructions.
Thus, instructions which are in a same issue group are concurrently forwarded (i.e. “issued”) to their respective execution units for execution in a same clock cycle. Accordingly, execution of all instructions in a VLIW packet may take as many clock cycles as there are issue groups in that VLIW packet. Referring to
FIG. 1
, one known technique for identifying the issue groups in a VLIW packet, such as VLIW packet
100
, is now discussed. As shown in
FIG. 1
, eight individual instructions in VLIW packet
100
are placed in instruction slots
102
through
116
. More specifically, instruction 0 is placed in instruction slot
102
, instruction 1 is placed in instruction slot
104
, instruction 2 is placed in instruction slot
106
, instruction 3 is placed in instruction slot
108
, instruction 4 is placed in instruction slot
110
, instruction 5 is placed in instruction slot
112
, instruction 6 is placed in instruction slot
114
, and instruction 7 is placed in instruction slot
116
.
In this known technique for identifying the issue groups in VLIW packet
100
, a designated bit in each instruction slot
102
through
116
is used to identify the different issue groups in the VLIW packet. In the example shown in
FIG. 1
, the designated bit used for this purpose is isolated by a dashed line. For example, instruction slot
102
shows that the designated bit used for the purpose of identifying the issue group to which instruction 0 belongs is a “0”. Likewise, instruction slots
104
,
106
, and
108
show that the respective designated bits used for the purpose of identifying the issue groups to which instructions 1, 2, and 3 respectively belong are all “0”. Instruction slot
110
shows that the designated bit used for the purpose of identifying the issue group to which instruction 4 belongs is a “1” while instruction slot
112
shows that the designated bit used for the purpose of identifying the issue group to which instruction 5 belongs is a “0”. Finally, instruction slots
114
and
116
show that the respective designated bits used for the purpose of identifying the issue groups to which instructions 6 and 7 respectively belong are both
According to this known technique for specifying and identifying issue groups, when the designated bit in a particular instruction is a “0”, that instruction is the last instruction in the issue group. Referring to the above example, instructions 7 and 6 are in the same issue group with instruction 5 which is the last instruction in that issue group. The reason is that the designated bit in instruction 5 is a “0”. Instructions 4 is in the same issue group with instruction 3 which is the last instruction in that issue group. The reason is that the designated bit in instruction 3 is a “0”. Instruction 2 is the first and last instruction in an issue group by itself. The reason is that the designated bit in instruction 2 is a “0”. Likewise, instruction 1 is in an issue group by itself and the same is the case for instruction 0. The reason is that the respective designated bits in instructions 1 and 0 are both “0”.
Thus, as shown in
FIG. 1
, instructions 7 through 5 are in an issue group referred to by numeral
118
; instructions 4 and 3 are in an issue group referred to by numeral
120
; instruction 2 is in an issue group by itself which is referred to by numeral
122
; instruction 1 is in an issue group by itself which is referred to by numeral
124
; and instruction 0 is in an issue group by itself which is referred to by numeral
126
. Accordingly, there are a total of five issue groups in the exemplary VLIW packet shown in FIG.
1
.
One disadvantage with the above-described known technique for specifying and identifying issue groups in a VLIW packet is that the VLIW processor must be designed to account for the possibility of existence of up to eight issue groups in each VLIW packet. Since each issue group takes one clock cycle for its execution, the VLIW processor must be designed to account for the possibility that it may take anywhere between one and eight clock cycles to complete the execution of all the individual instructions in a single VLIW packet. Manifestly, there is a large degree of uncertainty as to whether a VLIW packet fetched from the memory may take one, two, three, four, five, six, seven, or eight clock cycles for its execution. It also follows that the VLIW processor may have to “wait” anywhere between one and eight clock cycles before the processor can fetch another VLIW packet from the memory. It is also manifest that there is a large degree of uncertainty as to how many clock cycles the VLIW processor must “wait” before a new VLIW packet is fetched from the memory. The uncertainties associated with the number of clock cycles required for execution of a VLIW packet, and also number of clock cycles that the VLIW processor must wait, creates difficulties in designing hardware units such as the fetch and decode logic, the scheduling logic, and the data dependency checking logic of the VLIW processor.
Another disadvantage of the known technique described above is that eight bits must be used to identify the issue groups existing in the VLIW packet. In other words, even if there is merely one or two issue groups in that VLIW packet, eight bits must still be used to identify the issue groups in the VLIW packet. The fact that eight bits are used to identify the issue groups existing in a VLIW packet means that all of the eight individual instructions in a VLIW packet must be scanned in order to determine the existing issue groups in the VLIW packet. The reason is that the value of each respective designated bit in each instruction must be known in order to determine the issue groups existin
Li Chien-Wei
Mohamed Moataz A
Spence John R.
Farjami & Farjami LLP
Mindspeed Technologies Inc.
Treat William M.
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