Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-03-28
2003-06-17
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S261000, C327S262000, C327S269000, C327S270000, C327S276000, C327S152000, C327S153000, C327S158000, C327S161000
Reexamination Certificate
active
06580304
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronics and, more particularly, to apparatus and methods for introducing signal delay.
BACKGROUND OF THE INVENTION
Presently, there is a need for signal delay circuits capable of introducing a high precision delay to various signals. For example, in High Range Resolution (HRR) Radar systems, delay circuits are needed to generate intervals between transmit pulses and receive pulses with a resolution finer than 200 pico (p) seconds (s). Due to practical considerations, the delay circuits must be inexpensive, reliable, and small.
One well known method for generating a delay involves the use of a resistor and capacitor (RC) circuit. In an RC circuit, as the voltage applied to the RC circuit changes, the voltage across the capacitor gradually changes in a predictable manner to match the new voltage applied to the RC circuit. The time it takes the capacitor to transition from one voltage level to another voltage level in response to a predetermined change in the applied voltage level defines a predictable time interval, which may be used to generate a delay. Although inexpensive, this method is susceptible to noise that adversely affects its reliability.
Another method for generating a signal delay is depicted in FIG.
1
.
FIG. 1
is a block diagram of a known tapped delay locked loop (TDLL)
10
for shifting the phase of a periodic input signal. The TDLL
10
includes a delay chain
12
with (N) identical delay elements
14
, a comparator
16
, and a multiplexer
18
. Typically, the delay elements are fabricated as a single integrated circuit (IC) on a silicon wafer. Therefore, the delay elements are essentially identical and will each introduce an equal amount of delay to a signal passing through them.
In operation, an input signal received at an input port (IN) of the TDLL
10
is passed simultaneously to one input port at the comparator
16
and through the delay chain
12
. After passing through the delay chain
12
, a delayed version of the input signal is fed back to the other input port of the comparator
16
where its phase is compared to the phase of the input signal. The comparator
16
produces an error signal that is fed to each of the delay elements within the delay chain
12
to control the amount of delay provided by each delay element. Since the delay elements are identical, applying the error signal to each delay element will adjust each delay element by an equivalent amount. The comparator
16
adjusts its output (the error signal) until its two inputs are equal, which occurs when the phase of the input signal matches the phase of the input signal as delayed by the delay chain
12
. This occurs when the delayed signal is delayed exactly one period of the input signal. When the phases match, after at least one period of the input signal, the TDLL
10
is “locked,” and the input signal as delayed by the delay chain
12
is identical to the received input signal delayed by one period of the input signal.
Each delay element within the delay chain
12
successively introduces delay to the input signal as it passes through the delay chain
12
, where each successive delay is commonly referred to as a “step.” If each of the delay elements within the delay chain
12
is “tapped,” each tap will produce a signal identical to the input signal delayed by a fraction of the period of the input signal. That fraction is given by the number of delay elements the input signal has passed through divided by the total number of delay elements (N) in the delay chain
12
. The multiplexer
18
is coupled to the taps of the individual delay elements and is used to select one of the taps in response to a selection signal received at a selection port (Sel) to provide a desired delay.
The TDLL
10
is capable of introducing a delay to a periodic input signal. However, since the TDLL
10
takes at least one period of the input signal to “lock,” it is not suitable for delaying individual (or variable period) pulses. In addition, each step produced within a period of the input signal requires an additional delay element. Accordingly, systems requiring a large number of steps (i.e., high resolution) will require a large number of delay elements. As the number of delay elements increases, however, it becomes increasingly difficult to ensure that the individual delay elements will match, thus adversely affecting linearity.
FIG. 2
is a block diagram of a known “Vernier-type” circuit
20
for shifting the phase of a periodic input signal with a high level of precision. The circuit
20
includes a first TDLL identical to the TDLL
10
of
FIG. 1
(with like elements being identically numbered) and a second TDLL
22
similar to the TDLL
10
of FIG.
1
. The second TDLL
22
includes a second delay chain
24
with (N−1) identical delay elements
26
, a second comparator
28
, and a second multiplexer
30
. Typically, the first and second delay chains
12
,
24
are fabricated on a silicon wafer, with the delay elements of the first delay chain
12
being essentially identical to each other and the delay elements of the second delay chain
22
being essentially identical to each other. The output of the first multiplexer
18
is used as the input signal to the second TDLL
22
. Therefore, the first TDLL
10
introduces a first delay, and the second TDLL
22
introduces a second delay to the input signal as delayed by the first TDLL
10
.
The Vernier-type circuit
20
of
FIG. 2
enables very fine step sizes with fewer delay elements than a single TDLL such as TDLL
10
. By connecting the first and second TDLLs
10
,
22
in series, a large number of steps can be achieved using a relatively small number of delay elements, thus enabling the delay elements to be more easily matched. The number of steps is given by the product of the number of delay elements (N) in the first delay chain
12
and the number of delay elements (N−1) in the second delay chain
24
. As long as the number of delay elements in the second delay chain
24
is either (N+1) or (N−1), the step size will be the period of the input signal divided by that product. For example, if N=16, the step size will be one input signal period/(16*15)=1/240. Accordingly, if the input signal is 100 MHZ, the delay will be approximately 40 ps per step [(1/100 MHZ)/(16*15)=41.7 ps]. In this example, only 31 delay elements are required to achieve 240 steps (15×16=240). A single TDLL such as the TDLL
10
of
FIG. 1
would require 240 delay elements to provide 240 steps.
FIG. 2A
is a table
32
depicting the delay steps associated with a Vernier-type circuit
20
having a first delay chain
12
with N delay elements (vertical axis) and a second delay chain
24
with N−1 delay elements (horizontal axis) where N=5. Thus, this circuit
20
provides 5*4=20 delay steps. Each delay element in the first delay chain
12
will introduce a delay step that is ⅕ (or 0.200) of an input signal period; and each delay element in the second delay chain
24
will introduce a delay step that is ¼ (or 0.250) of the input signal period. Accordingly, the circuit
20
is capable of introducing delays between 0.450 of an input signal period if the minimum delay is introduced by each delay chain
12
,
24
and 2.000 times the input signal period if the maximum delay is introduced by each delay chain
12
,
24
.
The delay steps of the Vernier-type circuit
20
are spread over two periods of the input signal. Therefore, some of the delay steps are time delays of a fraction of the input signal period and thus the delayed signal appears within one period of the input signal, while other delay steps are time delays of a fraction of the input signal period plus one entire period of the input signal and thus the delayed signal appears between one and two periods of the input signal. For example, as depicted in table
32
, delay steps identified by numerals
9
,
13
-
14
, and
17
-
19
introduce a delay that is a fraction of
Lam Tuan T.
M/A-Com Inc.
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