Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2008-01-08
2008-01-08
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
active
11182141
ABSTRACT:
An apparatus and method for interfacing a processor to one or more co-processors interface provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronously to the dual ported memory. Control logic monitors activity by the processor to alert the co-processors of communications by the processor written to the memory and otherwise allows the processor and co-processors to think they are interfacing directly with one another.
REFERENCES:
patent: 4692918 (1987-09-01), Elliott et al.
patent: 5195181 (1993-03-01), Bryant et al.
patent: 5313586 (1994-05-01), Rutman
patent: 5566170 (1996-10-01), Bakke et al.
patent: 5784582 (1998-07-01), Hughes
patent: 5805820 (1998-09-01), Bellovin et al.
patent: 5867704 (1999-02-01), Tanaka et al.
patent: 5870109 (1999-02-01), McCormack et al.
patent: 5938737 (1999-08-01), Smallcomb et al.
patent: 5953503 (1999-09-01), Mitzenmacher et al.
patent: 5987568 (1999-11-01), Adams et al.
patent: 5991713 (1999-11-01), Unger et al.
patent: 6014660 (2000-01-01), Lim et al.
patent: 6016512 (2000-01-01), Huitema
patent: 6046980 (2000-04-01), Packer
patent: 6052718 (2000-04-01), Gifford
patent: 6070191 (2000-05-01), Narendran et al.
patent: 6073168 (2000-06-01), Mighdoll et al.
patent: 6084878 (2000-07-01), Crayford et al.
patent: 6108703 (2000-08-01), Leighton et al.
patent: 6118814 (2000-09-01), Friedman
patent: 6247059 (2001-06-01), Johnson et al.
patent: 6295599 (2001-09-01), Hansen et al.
patent: 6334179 (2001-12-01), Curran et al.
patent: 6424658 (2002-07-01), Mathur
patent: 6438678 (2002-08-01), Cashman et al.
patent: 2002/0009079 (2002-01-01), Jungck et al.
patent: 2002/0065938 (2002-05-01), Jungck et al.
patent: 2002/0194291 (2002-12-01), Jungck et al.
patent: 0 865 180 (1998-03-01), None
patent: WO 98/17039 (1998-04-01), None
patent: WO 99/05584 (1999-02-01), None
patent: WO 99/09725 (1999-02-01), None
patent: WO 99/27684 (1999-06-01), None
patent: WO 99/60459 (1999-11-01), None
patent: WO 00/14938 (2000-03-01), None
patent: WO 00/27092 (2000-05-01), None
patent: WO 00/28713 (2000-05-01), None
John Pescatore, Gartner Analyst, “Commentary: Digging into the DNS foundation,” obtained at internet address, http:/
ews.cnet.com
ews/0-1005-202-2080091.html, Jul. 15, 2000.
Rainbow Technologies Products, “CryptoSwift eCommerce Accelerator,” obtained at internet address, http://http://isg.rainbow.com/products/cs—1.html, Aug. 5, 2000.
FlowWise Networks, Inc., “AutoRoute™ Automatic Configuration of Layer 3 Routing,” www.flowwise.com.
FlowWise, “Router Accelerator—RA 7000 from FlowWise,” obtained at internet address http://www.flowise.com/products/ra7000.htm.
Intel® IXP1200 Network Processor, obtained at internet address, http://developer.intel.com/design
etwork/ixp1200.htm.
Marshall Brain, How Stuff Works, “How Web Servers and the Internet Work,” obtained at internet address http://www.howstuffworks.com/web-server.htm.
Marshall Brain, How Stuff Works, “How Domain Name Servers Work,” obtained at internet address http://www.howstuffworks.com/dns.htm.
Curt Franklin, How Stuff Works, “How Routers Work,” obtained at internet address http://www.howstuffworks.com/router.htm.
Microsoft Corporation, Sep. 1998 “Introduction to TCP/IP,” obtained at internet address http://msdn.microsoft.com/library/backgrnd/html/tcpipintro.htm.
Robert Stone, “CenterTrack: An IP Overlay Network for Tracking DoS Floods,” Article Oct. 1, 1999, pp. 1-9.
Chapter 1 TCP/IP Fundamentals, obtained at internet address http://webdocs.sequent.com/docs/tcpoac01/ch—1.htm, pp. 1-28.
Cheng Wu, “Web Switching: A New Generation of Networking,” pp. 1-3.
ArrowPoint Communications™ Article, “A Comparative Analysis of Web Switching Architectures,” pp. 1-11.
ArrowPoint Communications™, Brochure, “The Top 12 Benefits of Content Intelligence.”
L. Peter Deutsch, “DEFLATE Compressed Data Format Specification,” May 1996.
Antaeus Feldspar, Article, “An Explanation of the Deflate Algorithm,” Sep. 11, 1997.
ArrowPoint Communications™ CDDCenter Vendor Listing, “ArrowPoint CS-50 Highlights” obtained at internet address http://www.cddcenter.com/arrowpoint.htm, May 21, 2000.
Peter Christy, Analyst Commentary, “When to Distribute Content—The Peters′ Principles,” obtained at internet address http://www.cddcenter.com/index.html, May 21, 2000.
Content Delivery 101: An Introduction to Content Distribution & Delivery.
CDDCenter, “How Do Caching and Content Delivery Really Differ?” obtained at internet address http://www.cddcenter.com/cachingvcontent.htm, pp. 1-4, May 21, 2000.
Internet Research Group “Infrastructure Application Service Providers,” Feb. 2000, pp. 1-7.
Peter Christy, Internet Research Group, “Content Delivery Architectures: Why Doesn't One Size Fit All?” pp. 1-12.
Steven Vonder Haar,Inter@ctiveWeek, Feb. 14, 2000, “Content Delivery Shifts To Edge of Net,” obtained at internet address http://www.zdnet.com/intweek/stories
ews/0,4164,2436865.00.html, Dated May 22, 2000.
David Willis, Network Computing, “The Content-Delivery Edge,” obtained at internet address http://www.networkcomputing.com/1103/1103colwillis.html, Dated May 22, 2000.
Phrack Magazine, “IP-spoofing Demystified (Trust-Relationship Exploitation)” vol. Seven, Issue Forty-Eight, File 14 of 18, pp. 1-9, obtained at internet address http://www.fc.net/phrack/files/p48/p48-14.html, Dated Jun. 5, 2000.
Eddie Mission, “What is Eddie?”, obtained at internet address http://www.eddieware.org/what.html, Dated Apr. 21, 2000.
Cisco Enterprise Solutions, “Quality of Service,” obtained at internet address http://www.cisco.com/warp/public/779/largeent/learn/technologies/qos/.
Cisco White Paper, “Delivering End-to-End Security in Policy-Based Networks,” obtained at internet address, http://www.cisco.com/warp/public/cc/pd
emnsw/cap/tech/deesp—wp.htm.
Technology Packeteer, obtained at internet address, http://www.packeteer.com/technology/index.cfm.
Overview Cisco Content Networking, obtained at internet address http://www.cisco.com/warp/public/cc
eso/ienesv/cxne/ccnov—ov.htm.
Overview Cisco Secure Policy Manager 2.0, obtained at internet address http://www.cisco.com/warp/public/cc/pd/sqsw/sqppmn/prodlit/secmn—ov.htm.
Alteon Web Systems, White Paper “Optimizing ISP Networks and Services with DNS Redirection,” Aug. 1999.
Alteon Web Systems, White Paper “Virtual Matrix Architecture Scaling Web Services for Performance and Capacity,” Apr. 2000.
Alteon Web Systems, White Paper, Questions and Answers, pp. 1-3.
3Com Technical Papers, Layer 3 Switching, May 1998.
Web Cache Communication Protocol Version 2, pp. C-1 to C-54.
RFC2267 Working Group- Denial of Service Counter Measures, Tele-conference Meeting Aug. 25, 2000, Moderator, Henry Teng of eBay.
Track-back Architecture General Requirements Version 0.1, Initial Draft submitted to Counter-DoS Solutions Working Group, Jul. 31, 2000, Edited by Bob Geiger, Recourse Technologies.
SwitchOn Networks, Inc., ClassiPI™ At-a-Glance.
C-Port™ A Motorola Company, C-5™ Digital Communications Processor, Product Brief, pp. 1-8, May 4, 2000.
Peder Jungck, “Building a Faster Cache Server” A Theoretical Whitepaper, Silicon Valley Internet Capital, pp. 1-19.
IXF1002 Dual Port Gigabit Ethernet MAC, Product Brief, Level One™ an Intel Company.
NetLogic Microsystems Product Overview.
Agere, Inc. “The Challenge for Next Generation Network Processors”, Sep. 10, 1999.
Philips Semiconductors' VMS747 Security Processor Overview.
Cisco Systems, Cisco 12000 Series GSR, “Performing Internet Routing and Switching at Gigabit
Jungck Peder J.
Najam Zahid
Nguyen Andrew T.
Brinks Hofer Gilson & Lione
Cloudshield Teechnologies, Inc.
Coleman Eric
Katz James L.
LandOfFree
Apparatus and method for interconnecting a processor to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for interconnecting a processor to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for interconnecting a processor to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3921115